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We are currently seeing a transformation in the automotive industry with a shift towards development of software-defined vehicles (SDV). This shift requires changes to processes, people, and technology. In this paper, we will present a DevSecOps platform for SDV to improve efficiency, reduce costs and improve time-to-market. A set of application security tools can be executed automatically in this consolidated development platform. As such, development teams can focus their time on coding while the development platform is used to perform automated testing, early and often in the development lifecycle. This approach allows automotive organizations to develop more secure, high-quality software. We will also discuss workflows, and changes to processes and organizational structure to allow for more streamlined development and better utilization of the development platform to improve the overall security posture in the organization.

Automotive E/E architectures are changing driven by the need to address the performance requirements of ADAS/AD, e-Mobility connected vehicles. System complexity is increasing as OEMs transition to the central compute and zonal architectures of the Software Defined Vehicle (SDV).

Automotive targeted, heterogenous SoCs with dedicated hardware acceleration are necessary to tackle new complex functions with greater efficiency and traditional Model-Based Design (MBD) flows also need to evolve. They must allow the software developer to have the tooling automatically generate efficient code on heterogeneous compute architectures. It is in the testing of the software that a virtual prototype (vECU) can play a key role in the development process by avoiding dependencies on hardware and capitalizing on the visibility and efficiency of debugging that comes with a purely virtual environment.

Through an EV software case study we show modeling and simulation of FOC-based motor control and MBD deployment to multiple cores of the Infineon AURIX? TC4x architecture. We show the use of AI (MLP) for sensorless position estimation and subsequent hardware optimized code for the ARC? EV based Parallel Processing Unit (PPU)

We conclude that an enhanced workflow of Virtual Processor-in-the-Loop (vPIL) and the Virtual Hardware-in-the-Loop (vHIL) phases executing with the vECU, reduces turnaround time for function developers so that it can scale with the demands of today¡¯s compute requirements.

The neural network models used in embedded real-time applications are evolving quickly. Transformer networks are a deep learning approach that has become dominant for natural language processing and Generative AI as well as other time-dependent, series data applications. Now, transformer-based deep learning network architectures are being applied to vision applications with state-of-the-art results compared to CNN-based solutions. In this presentation, we will introduce transformers and contrast them with the CNNs commonly used for vision tasks today. We will examine the key features of transformer model architectures and show performance comparisons between transformers and CNNs. We will conclude with insights on why we think transformers will become increasingly important for visual perception tasks.

Developers of SoCs are used to collecting coverage to prove functionally correct designs. RISC-V adds to that burden as developers of custom CPUs also have to prove the core itself is correct.

For an applications processor such as an RV64GC core, especially if the vector extension (V) is added, there are hundreds of instructions; each one requiring maybe 20-40 lines of system Verilog to provide instruction coverage. Creating this manually is error prone and time consuming, worse still it may need to be maintained as unratified specifications change.

Synopsys (through acquisition of Imperas technology) already has a description of every instruction to be able to execute it in their RISC-V reference model. Creating functional coverage from this description is relatively straightforward and can be automated.

There are still other architectural elements to cover, such as MMU, PMP, PMA, interrupts and debug mode. Bugs often occur in corner cases, and unless those cases are expressed in covergroups and coverpoints you cannot be confident that these have been tested.

This paper looks at two specific examples of using functional coverage to achieve high quality verification:

1)Dolphin Design extended the OpenHW Group CV32E40P core with the XPULP SIMD instructions. The Imperas flow was used to create functional coverage for these instructions.

2)The OpenHW Group CVW project is the first OpenHW RISC-V core with an MMU. CVW was seen as well tested before working with Imperas. However a number of issues were quickly found.

Developing a RISC-V based SoC, both hardware and software, requires a range of expertise and use of best known methods and technologies.? Synopsys provides solutions from the beginning of the project, architecting the SoC, through implementation including RISC-V processor IP and verification of self-built RISC-V processors, through to software development on the SoC.? Come to the Synopsys kiosk to see how Synopsys, your trusted resource for SoC development, is supporting the RISC-V community.??

As the RISC-V ecosystem continues to grow, so does the importance of high quality, fast reference models. These are used across the design process, from architectural exploration of custom instructions, to system modelling of complex multicore designs. With designs ever more driven by software, allowing early execution of the target software stack means easier development of customised hardware and reduced time to market. A new challenge with custom instructions is verification ¨C golden reference models are a key part to achieving successful verification and design closure. ?This talk covers how ImperasFPM Fast Processor Models from Synopsys can be used to meet all of these needs.?

The open-standard RISC-V instruction-set architecture (ISA) continues to pick up momentum as designers look for more flexibility and choice in their processor vendors. Leveraging decades of experience in developing processor IP, Synopsys¡¯ ARC-V? portfolio delivers high-quality, configurable and extensible processors with excellent PPA to meet diverse application requirements and handle the latest workloads. Learn how Synopsys ARC-V RISC-V based Processor IP enables designers to combine the growing RISC-V ecosystem with proven Synopsys IP including AI to accelerate time-to-market for their differentiated designs.?

Growing chip complexity, shorter time-to-market windows, and engineering talent shortages are making it difficult for companies and chip designers to keep pace with demand for increasing innovation. These challenges are driving the semiconductor industry to pursue rapid improvements in PPA, semiconductor yield, and productivity across all facets of chip development with AI technologies. We¡¯ll explore how Synopsys.ai is unleashing the power of AI with comprehensive generative AI, design optimization, and data analytics technologies across the entire stack.