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High-Speed SerDes IP 91³Ô¹ÏÍø

Synopsys' comprehensive high-speed SerDes IP portfolio with leading power, performance, and area, allows designers to meet the efficient connectivity requirements of high-performance computing SoCs for hyperscale data center, networking, and storage applications.

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<p><a href="/dw/ipdir.php?ds=dwc_112g_ethernet_phy">112G Ethernet PH<span style="font-family: inherit;">Y IP</span></a><span style="font-family: inherit;"> enables true long reach channels for up to 800G high-performance computing SoCs</span></p><p><span style="font-family: inherit;"><a href="/dw/ipdir.php?ds=dwc_56g_ethernet_phy">56G Ethernet PHY IP</a> addresses reach and performance of up to 400G Ethernet applications</span></p><p><span style="font-family: inherit;"><a href="/content/synopsys/en-us/designware-ip/interface-ip/die-to-die.html">Die-to-Die PHY IP</a>&nbsp;enables up to 112G XSR connectivity</span></p><p><span style="font-family: inherit;"><a href="/content/synopsys/en-us/designware-ip/interface-ip/multiprotocol-phys.html">Multi-Protocol PHYs</a> supports Ethernet, PCI Express, CCIX, CXL and more protocols</span></p><p><a href="/content/synopsys/en-us/designware-ip/interface-ip/pci-express.html">PCI Express PHY IP</a>&nbsp;enables high-performance, power-efficient connectivity for up to 64GT/s SoCs on advanced FinFET processes</p>

Comprehensive Portfolio

224G Ethernet PHY IP and 112G Ethernet PHY IP enable true long reach channels as part of the industry's first Complete 1.6T Ethernet IP Solution

56G Ethernet PHY IP addresses reach and performance of up to 400G Ethernet applications

Die-to-Die PHY IP for UCIe and 112G XSR

Multi-Protocol PHYs supports Ethernet, PCI Express, CCIX, CXL and more protocols

PCI Express PHY IP enables high-performance, power-efficient connectivity for up to 128GT/s SoCs on advanced FinFET processes

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<p>Webinar: <a href="/designware-ip/resources/webinars/overcoming-pcie6-integration-and-validation-challenges.html?cmp=disp_ip_misc_07_14_22_1549306_wbr_ww_pcie_hhs20">Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges</a></p><p>Webinar: <a href="https://attendee.gotowebinar.com/register/1388436214572543504?source=Synopsys">PCIe 6.0 From IP to Interconnect in High-Performance Computing</a></p><p>Webinar:?<a href="/content/synopsys/en-us/designware-ip/resources/webinars/minimize-latency-with-400g-800g-ethernet-ip.html">Keeping Latency to a Minimum with 400G/800G Ethernet IP</a></p><p>Webinar:?<a href="https://readytalk.webcasts.com/starthere.jsp?ei=1474205&amp;tp_key=82f85b7d37&amp;sti=web">Achieving Low Latency Die-to-Die Connectivity Using a Single Controller and PHY IP Solution</a></p><p>Webinar: <a href="https://readytalk.webcasts.com/starthere.jsp?ei=1466672&amp;amp;tp_key=bc58fabe78&amp;amp;sti=search">PCI Express 6.0 Design Considerations &amp; IP Implementation</a></p><p>Whitepaper: <a href="/dw/doc.php/wp/Evolution_of_Data_Center_Networking_Technology-IP_and_Beyond_wp.pdf">Evolution of Data Center Networking Technology ¡ª IP and Beyond</a></p>

Educational Content Covering a Wide Range of Topics to Keep You Up-to-Date

Webinar: How 100G 200G Electro-Optical Interfaces Enable Low Power, Low Latency Datacenters,

Webinar: Key MAC Considerations for the Road to 1.6T Ethernet Success

Whitepaper: ESD Co-Design for High-Speed SerDes in FinFET Technologies

Webinar: The Path to 1.6TbE with 224G Ethernet PHY IP

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Now Playing: 224G and 112G Ethernet PHY IP enable 800Gbps and beyond at DesignCon 2024

 

 

 

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getty 546824255, servers, data center, network

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The Controller Designers Need for 1.6 Terabits per Second Ethernet Interfaces

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