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Enabling a New Era of Innovation through Open Collaboration?
Synopsys is a premier member of and is a supporter of the growth and development of RISC-V, an open standard instruction set architecture (ISA) that is changing the processor landscape. Synopsys provides comprehensive, ready-to-use design, verification, and IP solutions that enable designers to harness the full potential of the flexible ISA in every RISC-V-based design.
Key Benefits
Fast Architecture-Driven PPA Optimization
Accelerate Time-to-Market
Enabling Secure and Reliable Designs
Robust RISC-V Processor IP & Toolchain
Synopsys 91³Ô¹ÏÍø for RISC-V?
Design, RTL Analysis & Optimization
Synopsys Fusion QuickStart Kits (QIKs) for Synopsys ARC-V? and SiFive?Intelligence? X280 and?Performance? P550 processor IP include implementation scripts, reference guides, and a baseline floorplan so designers don¡¯t need to start from scratch. Utilizing QIKs and leveraging the Synopsys Fusion Compiler??RTL-to-GDSII design product and Synopsys Design Space Optimization (DSO.ai?) AI application for chip design can accelerate the development of RISC-V-based SoC designs. ?
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RTL Architect is a multi-dimensional implementation prediction engine that enables RTL designers to predict the PPA and congestion impact of their RTL changes.
Verification
Synopsys is at the forefront of RISC-V verification with specialized solutions ImperasDV and STING for RISC-V processor and system-level verification. These combine with the industry-leading Synopsys VCS? simulation, VC Formal? and Verdi? debug tools for improved efficiency. Synopsys EDA flows, emulation, and virtual prototyping solutions further support RISC-V SoC verification. Additionally, Synopsys has published a reference methodology cookbook for Bluespec RISC-V cores and a related whitepaper about UVM coverage.
Processor IP
Synopsys ARC-V? Processor IP includes high-performance, mid-range, and ultra-low power RISC-V processor options, as well as functional safety versions, to deliver optimal power-performance efficiency for a broad range of application workloads. Synopsys ARC-V Processor IP is supported by the growing RISC-V ecosystem, giving developers a menu of choices to build a flexible environment with all the required development tools. Also supported is the trusted Synopsys MetaWare Development Toolkit, which includes all of the components needed to develop, debug and optimize embedded software for ARC-V Processor-based designs.
Related Products
Custom Processor Design
ASIP Designer helps teams build a custom RISC-V processor through architecture exploration. Key capabilities include rapid exploration of architectural choices, generation of an efficient C/C++ compiler-based software development kit that automatically adapts to every architectural change, and automatic generation of power and area-optimized, synthesizable RTL.
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Interface & Verification IP
Thousands of customers trust Synopsys IP in their SoCs, minimizing risk and accelerating time to market. Synopsys provides the industry¡¯s broadest portfolio of complete, silicon-proven IP solutions, with leading PPA and security for the most widely used interfaces such as?UCIe, HBM, Ethernet, PCI Express, ?CXL, ?CCIX, DDR, USB, MIPI, ?HDMI, and Bluetooth.
Cloud
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Synopsys Cloud
Synopsys Cloud is a software platform that enables delivery of EDA tools, IP and infrastructure for end-to-end chip design through a browser. With unlimited EDA software licenses by the minute plus features such as complete license management automation, enhanced analytics, and the availability of multi-vendor flows, the platform empowers you to design higher quality chips, faster. ?
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Synopsys Cloud offers a free trial of a RISC-V based sub-system reference design using rocket-core with Synopsys LPDDR and UART IP and access to industry-leading?Synopsys VCS? simulation and Synopsys Verdi? debug. Learn more.
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