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The Roots of RISC-V and How the Architecture is Shaped

RISC-V was originally developed at the University of California, Berkeley, in May 2010 for academic use, and it is based on stemming from at least four decades back. The first RISC-V chip tape-out happened in 2011. Once the ISA tech reports were published, the specification was essentially placed in the public domain. All of a design¡¯s software runs on a small core set of instructions in the RISC-V ISA. With optional extensions, designers can tailor the architecture for different end markets. Designers also can choose what they¡¯d like to use from the available features, rather than having to use the architecture¡¯s full feature set.

The current iteration of RISC-V is considered the fifth generation of processors built on the concept of the reduced instruction set computer (RISC). Member companies of RISC-V International collaborate to define the open-standard specification, helping to drive new pathways for processor innovation while advocating for new degrees of design freedom. The organization now has more than 3,800 members across 70 countries and has reported that, by the end of 2022, more than 10 billion chips with RISC-V cores had shipped.

There¡¯s now a growing ecosystem of companies developing solutions to support RISC-V. This industry collaboration will further evolve the architecture. Synopsys, already a member of RISC-V International, will be represented by Yankin Tanurhan, sr. vice president of engineering in the 91³Ô¹ÏÍø Group at Synopsys, as one of the newest members of the organization¡¯s board of directors. The governing board¡¯s members are elected to represent all classes of membership, helping to ensure that oversight of the standard is balanced. Said Calista Redmond, CEO of RISC-V International: ¡°As RISC-V adoption grows across a broad range of markets, the RISC-V International board of directors is integral in providing direction and leadership to move the standard forward. With Synopsys¡¯ expertise in delivering solutions for SoC designs supporting the architecture, the addition of Rob Aitken from Synopsys further strengthens our ability to chart the future of the RISC-V standard.¡±

Key Benefits of RISC-V

Since the RISC-V architecture provides simplified instructions to the processor for various tasks, it¡¯s easy to see why the standard is becoming so popular. Compared to complex instruction set computing (CISC), which uses a larger set of more complex instructions for multiple operations per instruction, RISC architectures execute a single instruction per clock cycle. Complex operations can be performed, but with a minimal set of instructions. As a result, ly.

With its modularity, flexibility, and extensibility, designers can use RISC-V to create thousands of potential custom processors with just the features suited for their target application¡ªand do so with relative speed. Whether the design is a simple embedded one or a large supercomputer, designers would start from the same base ISA. Easier software development also contributes to a faster overall design cycle.

Security remains a concern across many industries. To address these concerns, the RISC-V architecture comes with a variety of security features, typically available through open-source reference designs, software composition analysis tools, and security extensions. 

Who¡¯s Adopting RISC-V?

Initial RISC-V adoption was primarily in the embedded applications and microcontrollers spaces. Over the years, the open-source standard has continued to gain traction in a broad array of application areas such as automotive, data centers, and high-performance computing, with growing promise for AI workloads. Here¡¯s a look at key application areas where we¡¯re seeing strong adoption of the RISC-V architecture:

• Automotive: For automotive SoCs, RISC-V processors can help meet requirements for performance, power, cost, and security for systems including infotainment, advanced driver assistance, and communications.
• High-performance computing (HPC) and data centers: RISC-V cores are well suited for taking care of complex computational tasks with customized ISAs, and RISC-V extensions can support development of simple, secure, and flexible cores that deliver the energy efficiency needed for these applications.
• AI: AI chips tend to be heterogeneous, with designers opting for off-the-shelf processors where they can (with RISC-V being one of the choices) and focusing their expertise on developing high-performance, energy-efficient AI accelerators for tasks such as neural network processing and natural language processing.
• Wearables, industrial, IoT, and home appliances: This segment is marked by battery-operated designs and space constraints, making RISC-V processors ideal for meeting their power requirements.
• 5G mobile: RISC-V cores can be tailored for the performance demands of mobile designs such as smartphones, or they can be used as a component in a larger SoC to handle specific tasks in these devices.
• Aerospace and government: With its high reliability and security, RISC-V provides a good option for these systems, which must meet stringent requirements. 

What Does the Future Hold for RISC-V?

As adoption continues to grow, so too does the ecosystem¡ªand industry collaboration¡ªsupporting the RISC-V architecture. A number of notable collaborations has emerged. For example, the is a global consortium of prominent industry leaders whose mission is to accelerate open-source software development for the RISC-V architecture. Another venture taking shape in Germany, also with a noteworthy roster, aims to , with an initial focus on automotive applications. A indicates that semiconductor supply chain shortages that have hampered vehicle production in recent years are sparking interest in the standard by the automotive industry.

The growing popularity of RISC-V isn¡¯t surprising, given the choices the open-source architecture provides to designers who want to customize their RISC-V processor-based SoCs for differentiation. We cannot underestimate the role of choice in driving semiconductor design innovation forward.