BLOG 2 min read/Jan 21, 2025 BLOG Synopsys Bold Prediction: 50% of New HPC Chip Designs Will Be Multi-Die in 2025 By Shekhar Kapoor, Michael Posner Tags: Multi-Die System, Chip Design Insights, Design, 3DIC Compiler
BLOG 5 min read/Jan 09, 2025 BLOG Multi-Die Health and Reliability: Synopsys and TSMC Showcase UCIe Advances By Faisal Goriawalla, Yervant Zorian Tags: Multi-Die System, Silicon Lifecycle Management, Chip Design Insights, Interface IP, Silicon IP
BLOG 2 min read/Dec 05, 2024 BLOG Collaboration for Innovation: How Synopsys and TSMC are Advancing Chip Design By Sween Kang Tags: Multi-Die System, Chip Design Insights, Design, Manufacturing, Foundation IP, HPC, Data Center, Silicon IP, 3DIC Compiler
BLOG 4 min read/Sep 09, 2024 BLOG Synopsys Introduces Industry¡¯s First 40G UCIe IP Solution to Power High-Performance Multi-Die Designs By Manuel Mota Tags: Multi-Die System, Chip Design Insights, Interface IP, Silicon IP
BLOG 3 min read/Aug 08, 2024 BLOG UCIe 2.0 - Setting the Tone for Chiplet Interoperability By Prasad Subudhi K. S, Deepak Nagaria, Narasimha Babu G V L Tags: Verification Central, Multi-Die System, Verification IP, Verification
BLOG 4 min read/Jun 17, 2024 BLOG Synopsys and Alchip Collaborate to Streamline the Path to Multi-die Success with Soft Chiplets By Manmeet Walia, Erez Shaizaf, Manuel Mota Tags: Multi-Die System, Chip Design Insights
BLOG 5 min read/Jun 12, 2024 BLOG GUC Leverages 3DIC Compiler to Enable 2.5D/3D Multi-Die Package By Synopsys Editorial Staff, WeiHsun Liao Tags: Customer Spotlight, Multi-Die System, Chip Design Insights, Design, 3DIC Compiler
BLOG 3 min read/Apr 25, 2024 BLOG Want to Mix and Match Dies in a Single Package? UCIe Can Get You There By Michael Posner, Manuel Mota Tags: Multi-Die System, Chip Design Insights, Interface IP, Silicon IP
BLOG 4 min read/Mar 20, 2024 BLOG Faster, Higher Capacity Emulation and Prototyping for AI Workloads By Samskrut Konduru Tags: Multi-Die System, AI & Machine Learning, Product Spotlight, Prototyping, Chip Design Insights, Emulation, Verification
BLOG 8 min read/Mar 15, 2024 BLOG Industry Leaders Discuss ¡°Overcoming the Challenges of Multi-die Systems Verification¡± By Verification Expert Tags: Verification Central, Multi-Die System, Verification
BLOG 5 min read/Mar 06, 2024 BLOG Industry's First Verification IP for Arm AMBA CHI-G By Sudhanshu Rao Tags: Verification Central, Multi-Die System, Verification IP, Verification
BLOG 5 min read/Feb 22, 2024 BLOG Synopsys AMBA CHI C2C System Verification 91³Ô¹ÏÍø By Venkatesh Kudumula Tags: Verification Central, Multi-Die System, Verification IP, Verification
BLOG 4 min read/Jan 23, 2024 BLOG Avoiding Multi-Die System Re-spins with New Early Architecture Exploration Technology By Kamal Desai Tags: Multi-Die System, Chip Design Insights, Design, Platform
BLOG 5 min read/Jan 22, 2024 BLOG Can 3DHI Meet the Demands of Aerospace and Government Applications? By Kenneth Larsen, Ian Land, Rob Aitken Tags: Multi-Die System, Aerospace & Government, Chip Design Insights, Design
BLOG 8 min read/Dec 20, 2023 BLOG 2023 in Review: AI Takes Center Stage in the Eternal Quest for Innovation By Synopsys Editorial Staff Tags: Cloud, Multi-Die System, Machine Learning, AI & Machine Learning, Chip Design Insights
BLOG 4 min read/Dec 14, 2023 BLOG Synopsys and Intel Team Up on the First UCIe-Connected Chiplet-Based Test Chip By Manuel Mota Tags: Multi-Die System, Chip Design Insights, Interface IP, Silicon IP
BLOG 5 min read/Dec 13, 2023 BLOG What¡¯s Next for Multi-Die Systems in 2024? By Shekhar Kapoor Tags: Multi-Die System, Chip Design Insights
BLOG 5 min read/Nov 21, 2023 BLOG How Photonics Can Light the Way for Higher Performing Multi-Die Systems By Kenneth Larsen, Twan Korthorst Tags: Multi-Die System, Chip Design Insights, Design, Photonic
BLOG 7 min read/Oct 11, 2023 BLOG Ensuring the Health and Reliability of Multi-Die Systems By Randy Fish, Yervant Zorian, Manuel Mota, Guy Cortez Tags: Multi-Die System, AI & Machine Learning, Chip Design Insights, Design, HPC, Data Center
BLOG 6 min read/Oct 04, 2023 BLOG Industry Insights: How Collaboration Will Accelerate Adoption of Multi-Die Systems By Synopsys Editorial Staff Tags: Multi-Die System, Chip Design Insights
BLOG 4 min read/Sep 21, 2023 BLOG Samsung Foundry and Synopsys Accelerate Multi-Die System Design By Henry Sheng, Jennifer Pyon Tags: Multi-Die System, Product Spotlight, Chip Design Insights, Design
BLOG 7 min read/Sep 12, 2023 BLOG Five Key Techniques to Accelerate Software Bring-Up for Multi-Die Systems By Filip Thoen, Leonard Drucker, Vivek Prasad Tags: Multi-Die System, Chip Design Insights, Verification
BLOG 4 min read/Aug 22, 2023 BLOG Addressing Multi-Physics Effects for High-Performing Multi-Die Systems By Shekhar Kapoor, Kenneth Larsen Tags: Multi-Die System, Chip Design Insights, Design
BLOG 8 min read/Aug 03, 2023 BLOG Embracing Multi-Die Systems and Photonics for Aerospace and Government Applications By Jigesh Patel, Kenneth Larsen, Ian Land Tags: Multi-Die System, Aerospace & Government, Chip Design Insights, Photonic
BLOG 6 min read/Aug 01, 2023 BLOG Key Considerations for Addressing Multi-Die System Verification Challenges By Arturo Salz, Dr. Johannes Stahl Tags: Multi-Die System, Chip Design Insights, Verification
BLOG 4 min read/Jul 24, 2023 BLOG New Distributed Simulation Technology for Faster Simulation of Multi-Die Systems By Taruna Reddy Tags: Multi-Die System, Chip Design Insights, Verification
BLOG 7 min read/Jun 28, 2023 BLOG Developing the Blueprint for Multi-Die Systems with Virtual Prototyping Tools By Dr. Johannes Stahl, Tim Kogel Tags: Multi-Die System, Chip Design Insights, Verification, Virtual Prototyping
BLOG 5 min read/Jun 21, 2023 BLOG Designing Electrostatic Discharge (ESD) Protection for Monolithic SoCs and Multi-Die Systems By Dermott Lynch Tags: Multi-Die System, Chip Design Insights, Design, Design Technology Co-Optimization
BLOG 4 min read/Jun 13, 2023 BLOG Synopsys and AMD Collaboration Achieves Significant Milestones for EDA Workloads By Andy Tai, Ramesh Narayanaswamy Tags: Multi-Die System, Chip Design Insights, Design, Physical Implementation, Signoff, HPC, Data Center, Verification
BLOG 6 min read/May 23, 2023 BLOG How Multi-Die Systems Transform the Semiconductor Industry By Shekhar Kapoor Tags: Multi-Die System, Chip Design Insights
BLOG 4 min read/May 22, 2023 BLOG Designing Thermal Management 91³Ô¹ÏÍø for Multi-Die Systems By Synopsys Editorial Staff Tags: Multi-Die System, Chip Design Insights
BLOG 6 min read/May 18, 2023 BLOG How Semiconductor Companies Use Multi-Die Systems By Shekhar Kapoor Tags: Multi-Die System, Chip Design Insights
BLOG 6 min read/Apr 26, 2023 BLOG Celebrating the 76th Anniversary of the Transistor By Victor Moroz, Rob Aitken Tags: Multi-Die System, Chip Design Insights
BLOG 7 min read/Apr 25, 2023 BLOG Upgrading 3DIC Packaging for Faster AI Inference with PSMC By Kenneth Larsen Tags: Multi-Die System, Chip Design Insights, Design
BLOG 5 min read/Apr 13, 2023 BLOG SNUG Silicon Valley 2023: Catalyzing the Future for Our Smart Everything World By Rob van Blommestein Tags: Multi-Die System, AI & Machine Learning, Silicon Lifecycle Management, Test, Chip Design Insights, Design, Verification, Inside Synopsys
BLOG 4 min read/Apr 11, 2023 BLOG UCIe Standard: Benefits & Requirements Explained By Manuel Mota Tags: Multi-Die System, Chip Design Insights, Interface IP, Silicon IP
BLOG 4 min read/Mar 31, 2023 BLOG Discovering the Future of Multi-Die Systems By Shekhar Kapoor Tags: Multi-Die System, Chip Design Insights
BLOG 4 min read/Mar 17, 2023 BLOG UCIe PHY IP Tape-Out on TSMC N3E Process By Manuel Mota Tags: Multi-Die System, Chip Design Insights, Silicon IP
BLOG 3 min read/Feb 22, 2023 BLOG What are Multi-Die Systems? By Shekhar Kapoor Tags: Multi-Die System, Chip Design Insights
BLOG 5 min read/Feb 07, 2023 BLOG Boosting Chip Design & Verification with AI EDA Tools By Shankar Krishnamoorthy Tags: Multi-Die System, AI & Machine Learning, Chip Design Insights, Design, Verification
BLOG 4 min read/Jan 19, 2023 BLOG How Systems of Chips Take Us From Smart to Smarter? By Shankar Krishnamoorthy Tags: Multi-Die System, AI & Machine Learning, Chip Design Insights
BLOG 5 min read/Jan 17, 2023 BLOG Why 2023 Holds Big Promise for Multi-Die Systems? By Shekhar Kapoor, Michael Posner Tags: Multi-Die System, Chip Design Insights
BLOG 6 min read/Jan 03, 2023 BLOG 3 Key Technologies that Will Transform Electronic Design in 2023 By Sanjay Bali Tags: Cloud, Multi-Die System, Silicon Lifecycle Management, Chip Design Insights, Design, 3DIC Compiler
BLOG 10 min read/Dec 19, 2022 BLOG 2022's EDA & Chip Design Advancements? By Synopsys Editorial Staff Tags: Multi-Die System, AI & Machine Learning, Prototyping, Emulation, Interface IP, Inside Synopsys, Cloud, Chip Design Insights, Design, Automotive, HPC, Data Center, Silicon IP, Verification
BLOG 5 min read/Aug 22, 2022 BLOG How 3DICs Are Sparking a New Wave of Product Innovation By Shekhar Kapoor Tags: Multi-Die System, Chip Design Insights
BLOG 4 min read/Jul 12, 2022 BLOG Enhancing Chip Verification with AI & Machine Learning By Rob van Blommestein Tags: Multi-Die System, Static Verification, AI & Machine Learning, Product Spotlight, Debug, Chip Design Insights, Simulation, HPC, Data Center, Verification, Formal Verification
BLOG 5 min read/Jul 11, 2022 BLOG What is a SmartNIC? By Rita Horner Tags: Multi-Die System, AI & Machine Learning, Chip Design Insights, Design, Security IP, Foundation IP, HPC, Data Center, Silicon IP, Verification, 3DIC Compiler
BLOG 6 min read/Jun 16, 2022 BLOG Data Center Journey: Data Volume Growth & Moore's Law? By Mike Gianfagna Tags: Multi-Die System, AI & Machine Learning, Chip Design Insights, 5G Wireless, HPC, Data Center
BLOG 6 min read/Feb 16, 2022 BLOG How to Design SoCs for the SysMoore Era? By Dr. Ming Zhang Tags: Multi-Die System, AI & Machine Learning, Chip Design Insights, Design, 3DIC Compiler
BLOG 2 min read/Dec 15, 2021 BLOG Hyper-Convergent Chip Designs: News & Trends? By Synopsys Editorial Staff Tags: Multi-Die System, Chip Design Insights, Design, HPC, Data Center
BLOG 4 min read/Nov 29, 2021 BLOG What is Democratized Design? - Chip Design Process By Synopsys Editorial Staff Tags: Multi-Die System, Chip Design Insights, Design
BLOG 5 min read/Sep 14, 2021 BLOG High-Performance Computing Drives Demand for Chiplets By Kenneth Larsen Tags: Multi-Die System, Chip Design Insights, Design, Interface IP, HPC, Data Center, Silicon IP
BLOG 5 min read/Aug 09, 2021 BLOG What is a Multi-Die Chip Design? By Kenneth Larsen, Manuel Mota Tags: Multi-Die System, Chip Design Insights, Design, Interface IP, Silicon IP
BLOG 5 min read/Jul 13, 2021 BLOG 3DIC Design Optimization for Power, Performance & Area? By Kenneth Larsen Tags: Multi-Die System, Chip Design Insights, Design
BLOG 4 min read/Jun 02, 2021 BLOG Die-to-Die Interfaces for Data Centers Bandwidth & Latency? By Manuel Mota Tags: Multi-Die System, Chip Design Insights, Interface IP, HPC, Data Center, Silicon IP
BLOG 3 min read/Apr 20, 2021 BLOG Library Characterization Tool for Advanced Node SoC Design? By Umang Doshi Tags: Multi-Die System, Product Spotlight, Chip Design Insights, Design, Signoff
BLOG 5 min read/Apr 19, 2021 BLOG PrimeSim Continuum's Enables IC Hyperconvergence? By Tom Hsieh Tags: Multi-Die System, AI & Machine Learning, Product Spotlight, Chip Design Insights, Design
BLOG 4 min read/Apr 14, 2021 BLOG FPGA Prototyping Powers the SoC Design & Verification Process By Dr. Johannes Stahl Tags: Multi-Die System, AI & Machine Learning, Product Spotlight, Prototyping, Chip Design Insights, Design, 5G Wireless, Verification
BLOG 4 min read/Apr 06, 2021 BLOG Integrated Chip Design Tools for IC Hyperconvergence By Raja Tabet, Anand Thiruvengadam Tags: Multi-Die System, AI & Machine Learning, Chip Design Insights, Design, HPC, Data Center, Silicon IP
BLOG 5 min read/Mar 03, 2021 BLOG How 3DIC Design Tools Enhance Productivity & Performance? By Shekhar Kapoor, Kenneth Larsen Tags: Multi-Die System, Chip Design Insights, Design, 3DIC Compiler
BLOG 7 min read/Nov 30, 2020 BLOG Die-to-Die Connectivity for High-Performance Computing? By Scott Durrant Tags: Multi-Die System, Chip Design Insights, HPC, Data Center, Silicon IP
BLOG 4 min read/Oct 20, 2020 BLOG Defining the AI Era with the IBM Research AI Hardware Center? By Arun Venkatachar Tags: Multi-Die System, AI & Machine Learning, Emulation, Interface IP, Virtual Prototyping, Chip Design Insights, Design, Manufacturing, Design Technology Co-Optimization, Processor 91³Ô¹ÏÍø, Silicon IP, Verification, 3DIC Compiler