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Unleash Maximum Throughput

Hyperscale data centers need access to ultra-efficient interfaces to support multi-trillion parameter AI compute models. Synopsys¡¯ UALink IP solution offers maximum throughput per lane at 200 Gbps, providing the performance needed to scale-up to 1,024 AI accelerator links. Consisting of controller, PHY, and verification IP, the complete UALink IP solution is engineered for data-intensive AI workloads offering low latency, high bandwidth, and advanced memory sharing capabilities. Built on decades of design experience in high-speed PCIe and Ethernet IP, Synopsys¡¯ UALink IP reduces integration risk and speeds time to market for AI and HPC chip designers unleashing next-gen AI infrastructures. 

Key Benefits

Features

  • Lightweight, low latency IP solution for XPU to XPU interconnects optimized for AI workloads
  • Fully integrated IP solution for AI accelerators (XPUs), GPUs, and switches
  • Enables maximum throughput with up to 200Gbps per lane
  • Supports memory sharing capabilities to expand compute and memory resources from XPU to XPU
  • Supports high density, high radix networking infrastructure for AI workloads
  • Enables full hardware security needs for UALink specifications
Synopsys UALink IP Solution

News and Blogs

Related Products and 91³Ô¹ÏÍø

Synopsys provides the industry¡¯s broadest IP portfolio for HPC and AI, enabling designers with best-in-class IP interfaces so designers can speed time to market and achieve first pass silicon success.

Resources

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Synopsys 224G IP Solution Shows Widest Multi-Vendor Interop at ECOC 2024

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Synopsys 800G MAC, PCS and PHY IP Interop with Switches and Optical Links at ECOC 2024

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World's First PCIe 7.0 Controller IP Demonstration at PCI-SIG DevCon 2024

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PCIe 7.x, PCIe 6.x and 224G Over Optics at OFC 2024