91³Ô¹ÏÍø

Synopsys PCI Express (PCIe) IP 91³Ô¹ÏÍø

PCIe, PCIe IP, PCI Express

Overview

Synopsys IP 91³Ô¹ÏÍø for PCI Express? (PCIe?) consist of digital controllers, Integrity and Data Encryption (IDE) Security Modules, PHYs and verification IP. The IP solutions are designed to support all required features of the PCIe 7.0 128GT/s (Gen7),  PCIe 6.x 64GT/s (Gen6), PCIe 5.0 32GT/s (Gen5), PCIe 4.0 16GT/s (Gen4), 3.1 8GT/s (Gen3), 2.1 5GT/s (Gen2) and 1.1 2.5GT/s (Gen1), and latest PIPE specifications. 

As the leading supplier of PCIe IP, Synopsys offers silicon-proven IP solutions for PCIe that provide high-throughput, low-latency, and power-efficient external connectivity in SoCs for mobile, networking, storage, cloud computing, AI, and automotive applications. Extensive interoperability testing with third-party products and strict quality measures combined with an expert technical support team enables designers to accelerate time-to-market and reduce integration risk.

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Synopsys Demonstrates Industry¡¯s First Interoperability of PCI Express 6.x IP with Intel¡¯s PCIe 6.x Test Chip

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PCIe 6.x Simulation and Electrical Testing for High Data-Bandwidth Applications

<p>PCIe, the most popular interconnect in compute, AI and storage systems, is now offering faster data rate, higher performance, lower power and lower latency than the previous generation. Because of these reasons and the addition of PAM-4 signaling, challenges such as signal integrity, power integrity, implementation, IP integration and more must be considered when designing 64GT/s systems.</p>

How to Maximize PCIe 6.x¡¯s Advantages with End-to-End PCIe Design 91³Ô¹ÏÍø

<p>PCIe, the most popular interconnect in compute, AI and storage systems, is now offering faster data rate, higher performance, lower power and lower latency than the previous generation. Because of these reasons and the addition of PAM-4 signaling, challenges such as signal integrity, power integrity, implementation, IP integration and more must be considered when designing 64GT/s systems.</p>

Leveraging IBIS-AMI Models to Optimize PCIe 6.x Designs


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