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Synopsys enables multi-die designs with a comprehensive die-to-die IP solution that includes UCIe and 112G XSR controller, PHY, and verification IP. The UCIe PHY, adopted by leading companies, has achieved several silicon successes across multiple foundry processes. Operating at 40Gbps, the IP delivers maximum die-edge and power efficiency, low latency, and support for standard and advanced packaging technologies, while being compliant with the latest UCIe specification. The UCIe controller enables an ultra-low latency link between dies based on popular protocols to ensure interoperability. The Synopsys 112G XSR IP leverages high-speed SerDes technology for extra short reach links. The XSR controller includes a highly optimized FEC for a reliable, low latency link between dies.