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Many of us almost take for granted that we can stream a high-definition movie on our smartphones as we take the commuter train into the office. Or that artificial intelligence (AI) and machine learning (ML) have made it possible for data analytics systems to generate more accurate insights with greater efficiency. None of this can happen, however, without powerful server processors that can run the compute-intensive electronic design automation (EDA) workloads required to develop the massively complex SoCs enabling these applications.
This is why the performance enhancements that result from continued collaboration between Synopsys and AMD are so impactful for designing, testing, and manufacturing semiconductor products. The launch of the 4th Gen AMD EPYC? processors with AMD 3D V-Cache? technology is marked by performance achievements that are great news for a smart everything world that is demanding more and more from silicon chips. Some key points to note:
- Simulation workloads using Synopsys VCS? functional verification solution run 1.2x faster on AMD EPYC 9004 Series processors versus the preceding AMD EPYC processor family with AMD 3D V-Cache technology
- Digital design and analog workloads using Synopsys PrimeSim? circuit simulation solution, Synopsys Fusion Compiler? physical implementation solution, and Synopsys PrimeTime? static timing analysis solution run 1.2x to 1.4x faster versus the preceding AMD EPYC processor family with AMD 3D V-Cache technology
Mutual customers¡ªwhether they¡¯re developing monolithic SoCs or multi-die systems for high-performance computing (HPC) applications¡ªcan enjoy a processing speed-up that will enable them to, ultimately, achieve faster time to market of their designs. The newest AMD EPYC processors provide a robust energy- and space-efficient environment to run the most demanding enterprise applications, including EDA.
Demands of Data-Driven Chip Designs
HPC applications are swimming in petabytes of data (and growing), and the data itself is also becoming more complex. To generate the insights and outcomes anticipated from these applications¡ªand often, in real time¡ªhyperscale data centers require server chips that can support the capacity while delivering blazingly fast processing speeds. In many cases, monolithic SoCs are not sufficient, leading hyperscalers turn to multi-die systems. Delivering heterogeneous integration of dies in a single package, a multi-die system provides efficient scaling of system functionality, as well as reduced risk and time to market, lower power, and faster creation of product variants. From a verification standpoint, a multi-die system is simply that much more massive in size, requiring a speed-up in the process and leading-edge distribution technologies to effectively partition and ensure aggressive time-to-market goals are met.
AMD EPYC 9004 Series processors are one of the highest performance server processors for technical computing, handling workloads including EDA, computational fluid dynamics (CFD), and finite element analysis (FEA). The CPUs are built on 3D die stacking architecture ¡ª known as AMD 3D V-Cache ¡ª with copper-to-copper bonds (no solder bumps) on a 5nm process technology. With more than 200x the interconnect densities of typical 2D CPU technologies, the processors are designed to relieve memory bandwidth pressure and reduce latency. AMD 3D V-Cache technology provides dramatic, out-of-the-box performance uplifts across an array of workloads, including commercial HPC applications.
¡°Chip designers continue to face a trifecta of challenges stemming from the demands of data-intensive applications, including greater performance, more energy efficiency, and lower costs for their essential technical compute workloads,¡± said Shankar Krishnamoorthy, GM of the EDA Group at Synopsys. ¡°Our longstanding collaboration with AMD delivers performance optimization of Synopsys flows, capitalizing on AMD EPYC processors with 3D V-Cache technology to enable the faster turnaround times our customers need to accelerate their time to market.¡±
¡°4th Gen AMD EPYC processors with AMD 3D V-Cache technology build on AMD technical computing leadership, providing the design and packaging technology needed to address demanding CFD, FEA, and EDA workloads,¡± said Ravi Kuppuswamy, corporate vice president, Server 91³Ô¹ÏÍø Group at AMD. ¡°With our AMD 3D V-Cache technology, customers can take advantage of the 4th Gen AMD EPYC processor¡¯s leadership performance and energy efficiency to enhance the productivity of the teams running complex design, verification, and simulation, driving faster time to market for new products and technologies.¡±
Indeed, simulation is one of the most bandwidth-intensive EDA flows and, as such, benefits greatly from the performance boost provided by AMD 3D V-Cache. The Synopsys VCS functional simulation solution, the industry¡¯s highest performance in its class, can take full advantage of the additional cache in the new processor (1150MB of L3 cache), as well as the additional bandwidth support (12 DDR5 channels). The processors feature up to 96 high-performance AMD ¡®Zen 4¡¯ cores with 12 MB L3 cache per core and 4.7GB/s memory bandwidth per core. The high core count lends itself to fine-grained parallel simulation, which speeds up long-running simulations.
The high core counts available from AMD EPYC 9004 processors support multi-threaded workloads that are distributed and simultaneously processed across multiple cores for faster turnaround times. The larger models tied to Synopsys VCS and Synopsys PrimeSim technologies benefit from the core density. For example, Synopsys VCS running on the processor has demonstrated a verification throughput result of 90+ single core simulations per socket.
Enhancing EDA Performance for Demanding Workloads
Digital design and verification workloads are growing larger as chips expand in size (or take on multi-die architectures). Yet, time-to-market goals continue to be aggressive. 4th Gen AMD EPYC processors with AMD 3D V-Cache technology are ready to take on the demands, delivering scalable performance as well as energy efficiency for cloud-native computing workloads. Through our longstanding collaboration with AMD, Synopsys digital design and verification flows are optimized to run on AMD EPYC 9004 processors, enabling chip designers to do more with their engineering resources and with greater energy efficiency.
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