BLOG 4 min read/Jul 09, 2024 BLOG How to Use Python to Customize PrimeTime By Manoz Palaparthi Tags: Chip Design Insights, Design, Signoff
BLOG 2 min read/Apr 18, 2024 BLOG Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud By Anuj Pant Tags: Customer Spotlight, Cloud, Chip Design Insights, Design, Physical Implementation, Signoff
BLOG 3 min read/Mar 05, 2024 BLOG CalligoTech Enables Next-Gen Computing at Scale with Synopsys Digital Design Flow By Karan Shah, Irfan Shaikh Tags: Customer Spotlight, RTL Synthesis, AI & Machine Learning, Physical Verification, Test, Chip Design Insights, Design, Physical Implementation, Signoff, HPC, Data Center
BLOG 4 min read/Jun 13, 2023 BLOG Synopsys and AMD Collaboration Achieves Significant Milestones for EDA Workloads By Andy Tai, Ramesh Narayanaswamy Tags: Multi-Die System, Chip Design Insights, Design, Physical Implementation, Signoff, HPC, Data Center, Verification
BLOG 3 min read/May 04, 2023 BLOG Synopsys Acquires Silicon Frontline Technology By Synopsys Editorial Staff Tags: Chip Design Insights, Design, Energy-Efficient SoCs, Signoff, Inside Synopsys
BLOG 4 min read/Nov 02, 2022 BLOG Library Characterization for Advanced Process Chip Designs? By Moninder Bansal Tags: Product Spotlight, Chip Design Insights, Design, Signoff
BLOG 7 min read/Oct 27, 2022 BLOG Why Sacrifice QoRs? Optimizing Design Signoff and Achieving Accurate Functional ECOs the Smarter Way By Makarand Patil, Avinash Palepu Tags: Product Spotlight, Chip Design Insights, Design, Signoff
BLOG 4 min read/Sep 27, 2022 BLOG Unifying Timing Constraints with FishTail Design Automation? By Synopsys Editorial Staff Tags: Chip Design Insights, Design, Signoff, Verification
BLOG 4 min read/Sep 14, 2022 BLOG Enabling Edge Machine Learning Applications with SiMA.ai? By Stelios Diamantidis Tags: Customer Spotlight, RTL Synthesis, AI & Machine Learning, Chip Design Insights, Design, Emulation, Signoff, Silicon IP, Verification
BLOG 6 min read/Aug 09, 2022 BLOG Accelerate SoC Design Flow with Functional ECO? By Makarand Patil, Avinash Palepu Tags: Product Spotlight, Chip Design Insights, Design, Signoff
BLOG 4 min read/Feb 08, 2022 BLOG Powering Circuit Simulation Software with NVIDIA GPUs? By Samad Parekh Tags: Customer Spotlight, Chip Design Insights, Design, Signoff, Customer
BLOG 4 min read/Sep 08, 2021 BLOG EDA Tools Help Students Build IC Design Skills? By Synopsys Editorial Staff Tags: Custom Implementation, Physical Verification, Chip Design Insights, Design, Signoff, Inside Synopsys
BLOG 2 min read/Aug 19, 2021 BLOG Improving Design Robustness with PrimeShield: A Discussion with Li Ding By Synopsys Editorial Staff Tags: Design, Signoff, Inside Synopsys
BLOG 5 min read/Jul 06, 2021 BLOG How Emulation Helps Find Power Bugs During SoC Verification? By Alex Wakefield Tags: Static Verification, Chip Design Insights, Simulation, Design, Emulation, Energy-Efficient SoCs, Signoff, Verification, Virtual Prototyping, Formal Verification
BLOG 3 min read/Jun 28, 2021 BLOG Resistance Extraction with StarRC By Senthil Annamalai Tags: Design, Signoff
BLOG 4 min read/Apr 29, 2021 BLOG PrimeLib? Next-Generation Library Characterization: A Discussion with Moninder Bansal By Synopsys Editorial Staff Tags: Design, Signoff, Inside Synopsys
BLOG 3 min read/Apr 20, 2021 BLOG Library Characterization Tool for Advanced Node SoC Design? By Umang Doshi Tags: Multi-Die System, Product Spotlight, Chip Design Insights, Design, Signoff
BLOG 4 min read/Mar 16, 2021 BLOG Emulation Technology for Faster SoC Power Verification? By Dr. Johannes Stahl Tags: AI & Machine Learning, Chip Design Insights, Design, Emulation, 5G Wireless, Energy-Efficient SoCs, Signoff, Verification
BLOG 2 min read/Feb 18, 2021 BLOG StarRC Standalone Netlist Reducer: Achieving Practical Simulation Times By Senthil Annamalai Tags: Design, Signoff
BLOG 2 min read/Aug 25, 2020 BLOG StarRC Density Corner Value Proposition By Nitin Kalra Tags: Design, Signoff