Jul 09, 2024/4 min read How to Use Python to Customize PrimeTime By Manoz Palaparthi Tags: Chip Design Insights, Design, Signoff
Apr 18, 2024/2 min read Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud By Anuj Pant Tags: Customer Spotlight, Cloud, Chip Design Insights, Design, Physical Implementation, Signoff
Mar 05, 2024/3 min read CalligoTech Enables Next-Gen Computing at Scale with Synopsys Digital Design Flow By Karan Shah, Irfan Shaikh Tags: Customer Spotlight, RTL Synthesis, AI & Machine Learning, Physical Verification, Test, Chip Design Insights, Design, Physical Implementation, Signoff, HPC, Data Center
Jun 13, 2023/4 min read Synopsys and AMD Collaboration Achieves Significant Milestones for EDA Workloads By Andy Tai, Ramesh Narayanaswamy Tags: Multi-Die System, Chip Design Insights, Design, Physical Implementation, Signoff, HPC, Data Center, Verification
May 04, 2023/3 min read Synopsys Acquires Silicon Frontline Technology By Synopsys Editorial Staff Tags: Chip Design Insights, Design, Energy-Efficient SoCs, Signoff, Inside Synopsys
Nov 02, 2022/4 min read Library Characterization for Advanced Process Chip Designs? By Moninder Bansal Tags: Product Spotlight, Chip Design Insights, Design, Signoff
Oct 27, 2022/7 min read Why Sacrifice QoRs? Optimizing Design Signoff and Achieving Accurate Functional ECOs the Smarter Way By Makarand Patil, Avinash Palepu Tags: Product Spotlight, Chip Design Insights, Design, Signoff
Sep 27, 2022/4 min read Unifying Timing Constraints with FishTail Design Automation? By Synopsys Editorial Staff Tags: Chip Design Insights, Design, Signoff, Verification
Sep 14, 2022/4 min read Enabling Edge Machine Learning Applications with SiMA.ai? By Stelios Diamantidis Tags: Customer Spotlight, RTL Synthesis, AI & Machine Learning, Chip Design Insights, Design, Emulation, Signoff, Silicon IP, Verification
Aug 09, 2022/6 min read Accelerate SoC Design Flow with Functional ECO? By Makarand Patil, Avinash Palepu Tags: Product Spotlight, Chip Design Insights, Design, Signoff
Feb 08, 2022/4 min read Powering Circuit Simulation Software with NVIDIA GPUs? By Samad Parekh Tags: Customer Spotlight, Chip Design Insights, Design, Signoff, Customer
Sep 08, 2021/4 min read EDA Tools Help Students Build IC Design Skills? By Synopsys Editorial Staff Tags: Custom Implementation, Physical Verification, Chip Design Insights, Design, Signoff, Inside Synopsys
Aug 19, 2021/2 min read Improving Design Robustness with PrimeShield: A Discussion with Li Ding By Synopsys Editorial Staff Tags: Design, Signoff, Inside Synopsys
Jul 06, 2021/5 min read How Emulation Helps Find Power Bugs During SoC Verification? By Alex Wakefield Tags: Static Verification, Chip Design Insights, Simulation, Design, Emulation, Energy-Efficient SoCs, Signoff, Verification, Virtual Prototyping, Formal Verification
Apr 29, 2021/4 min read PrimeLib? Next-Generation Library Characterization: A Discussion with Moninder Bansal By Synopsys Editorial Staff Tags: Design, Signoff, Inside Synopsys
Apr 20, 2021/3 min read Library Characterization Tool for Advanced Node SoC Design? By Umang Doshi Tags: Multi-Die System, Product Spotlight, Chip Design Insights, Design, Signoff
Mar 16, 2021/4 min read Emulation Technology for Faster SoC Power Verification? By Dr. Johannes Stahl Tags: AI & Machine Learning, Chip Design Insights, Design, Emulation, 5G Wireless, Energy-Efficient SoCs, Signoff, Verification
Feb 18, 2021/2 min read StarRC Standalone Netlist Reducer: Achieving Practical Simulation Times By Senthil Annamalai Tags: Design, Signoff