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Traditionally Capacitance was the main extracted parasitic element and technology for capacitance extraction progressed rapidly. Resistance extraction was done primarily by rule-based technique since metal traces only supported 90 deg turns. With recent advancements in silicon process technology and 3DIC packaging, all angle and curved traces are possible. To support all angle trace resistance extraction mesh technique is required and for curved trace resistance extraction field solver is needed. In this video you will learn about different resistance extraction techniques supported by StarRC.

Transcript:

Hi, my name is Senthil Annamalai. I'm a Senior Staff Product Engineer at Synopsys supporting extraction products. In this video, I'm going to cover the applications for StarRC's resistance extraction capabilities.
StarRC currently supports rule-based, mesh, and field solver approaches for resistance extraction. Traditionally, capacitance was the main extracted parasitic element, and technology for capacitance extraction progressed rapidly. This extraction is done primarily by rule-based techniques since metal traces only supported 90-degree turns.

Recent advancements in silicon process technology and 3DIC packaging now allow all-angle and curved traces. To support all-angle trace resistance extraction, a mesh technique is required. For curved trace resistance extraction, a field solver is needed, as shown in the image.

In the rule-based approach for resistance extraction, the extractor first decides the current direction based on heuristics. Then, along the current direction, it generates nodes and connects them by resistors whose values are calculated by RPSQ x L/W, where RPSQ is the resistance per square for the layer in which the resistance is extracted. L is the length and W is the width of the polygon. This approach is accurate enough for long rectangles with uniform widths and easily determined current direction. However, it is not accurate when the length-to-width aspect ratio is close to 1, making it hard to decide the current direction. This is especially true for designs with non-Manhattan shapes and holes.

Mesh-based extraction improves resistance extraction accuracy on complicated slotted metal layers where current flow is difficult to determine. The target layout condition is PG mesh extraction with plenty of slots and multiple layers. The standard mesh resistance analysis might require longer runtime than standard resistance analysis, and the netlist size increases due to the larger number of resistance nodes, impacting subsequent simulation runtime. Users may use parasitic reduction options to mitigate these effects.
The Resistance Field Solver (RFS) uses a refined mesh analysis approach for resistance calculation, providing accurate resistance extraction for any shape of geometries, including non-Manhattan shapes with many holes. To allow resistance calculation of planar arbitrarily shaped geometries, a 2.5D meshed approach is used. For 2.5D mesh, a single plane of resistive elements is created in the X-Y direction for each metal layer. Contacts in the Z-direction are then made to the mesh with additional resistors in the Z-direction only for vias. 2.5D simulation runs much faster than full 3D since the number of nodes is much smaller. The user can choose specific nets and/or layers for RFS to extract.

Ports provide connections between the RFS and the outside world. There are options to control how to model ports, specify the mesh size, and refine the mesh. Various modes of reduction are supported as well. Process models, including etch and thickness variations and various resistivity models, are accounted for in RFS.

StarRC is the Golden Signoff extraction tool with renewed focus on features for custom design. The addition of resistance field solver capability supports accurate resistance extraction on custom design traces for display driver ICs, automotive chips, and 3DICs.

Thank you for watching this video.