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Chip designers are often stuck between a rock and a hard place. Not only are they dealing with staggering design complexity, but they're also under pressure to accelerate time to market. Anything that can help increase design and development efficiency, decision making, and speed provides much-needed relief.
In recent years, relief has come in the form of artificial intelligence (AI).
Synopsys is a pioneer in AI-driven electronic design automation (EDA), and we recently bolstered the AI capabilities of our Fusion Compiler via native integration with DSO.ai. With dynamic, adaptive flows powered by AI, the solution is able to automate decision making, optimize power, performance, and area (PPA), and deliver faster, more effective results.
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Automating RTL-to-GDSII flows
Traditionally, large companies and design houses have centralized teams that create a single flow for all designs. Because these flows must cater to all design types, they¡¯re often overly complex for simpler design partitions and under-tuned for the most demanding design partitions. In addition, design teams must commit to specific application settings and have limited ability to adjust those settings as they progress through the design implementation process.
The new, AI-driven adaptive flow capability of Fusion Compiler solves these problems. It enhances Register-Transfer Level (RTL) to Graphic Data System II (GDSII) processes by dynamically adapting the design flow and engine heuristics based on real-time observations. The AI continuously monitors and adapts the flow to ensure design convergence ¡ª even when initial configurations prove less effective.
Instead of a rigid, pre-defined flow sequence, the AI intelligently and dynamically adapts the engines and flows based on the unique characteristics and challenges of the current design. Not only between major flow steps, but also within the sub-flow steps not accessible by external agents.
By continuously monitoring design metrics and trends, the AI can autonomously:
- Choose an alternative optimization heuristic or methodology.
- Execute selective optimization steps to reduce turnaround time.
- Rearrange sub-flow steps to improve convergence.
- Reinforce a sub-flow step to increase the effort level for a given design challenge.
- Recover from sub-optimal results by re-executing a previous step with an alternative approach.
Continuous learning and optimization
The AI driving the adaptive flow is pre-trained at the factory to deliver fast results and reduce compute requirements by 5-10x compared to general-purpose AI optimization applications. In addition to pre-training, the AI continues to learn once it is implemented.
As the AI monitors design flows and makes real-time adjustments, it learns from the outcome of every action taken. This improves the accuracy of AI-driven decisions and optimization over time.
What¡¯s more, the AI becomes even more effective when additional compute resources are available. By exploring multiple adaptive strategies in parallel, the AI can expand its learning space horizontally across all runs. This provides broader input and insight, helping the AI learn the best optimization strategies across every micro-step of every design implementation flow.
The AI¡¯s ability to fine-tune adjustments surpasses human capabilities, making it invaluable for both expert and less-experienced users.
Benchmarking performance improvements
While benchmarking the performance improvements of AI-driven flows against those orchestrated by expert engineers is challenging, our new adaptive flow has shown promising results. The latest release of Fusion Compiler demonstrated up to 7% improvement in power and 2% improvement in area utilizing just five compute resources.
For semiconductor companies with highly optimized flows for high-performance computing (HPC) or mobile design partitions, these enhancements could be game-changing for product quality and time to market. Across all users and applications, the new adaptive flow can deliver 2-3x faster time-to-PPA-target than existing flows. Our customers who piloted the new adaptive flow have not only experienced significant improvements in PPA, but also ease of deployment, reduced compute, and improved process optimization.
Accelerating chip design flows with AI
Powered by AI, the new adaptive flow capability of Fusion Compiler represents a significant leap forward in chip design and development. By dynamically adjusting and optimizing design flows and engine heuristics based on real-time observations, it promises to deliver better performance, design efficiency, and time to market. And as it learns and evolves over time, it will deliver compounding benefits and continue to redefine the future of chip design.
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5 min read
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Apr 10, 2025
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