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First-Pass Silicon Success on TSMC¡¯s N2 Process Will Enable New Generation of AI-Enabled Edge Devices

Hezi Saar

Apr 23, 2025 / 3 min read

Recently, Synopsys IP achieved first-pass silicon success on TSMC¡¯s N2 process. This achievement is a major step forward in the development of next generation AI-enabled systems ¡ª especially mobile and other edge devices. It will also help accelerate the industry¡¯s transition from FinFET to nanosheet architecture, which supports increased chip performance and power efficiency.

For more than 20 years, Synopsys and TSMC have collaborated to provide the industry¡¯s broadest portfolio of interface and foundation IP for TSMC¡¯s advanced process technologies. This first-pass silicon success on TSMC¡¯s 2nm technology with nanosheet transistor structure exemplifies the strengths and innovation of our longstanding partnership.

2nm-nanosheet-gaa-process-eye-diagram

Edge AI and mobile computing are driving the transition to nanosheet designs

Despite significant investments in new silicon for AI training, mobile devices remain the biggest volume driver for silicon foundries. Mobile and edge device manufacturers introduce new, more capable products in regular intervals, and there¡¯s no slack in the schedule when it comes to delivering semiconductors to support these launches.

Because of the significant benefits of running AI locally, the next frontier in mobile and edge innovation will be the ability to run more powerful AI models ¡ª directly on the device. 

As developers and manufacturers seek to run larger and more complex Mixture of Experts (MoE) models and AI agents on mobile and edge devices, they often encounter issues related to performance, heat, and power. As a result, on-device AI models are currently limited to less than 10B parameters.

But advances are being made on multiple fronts. More capable and compact AI models are being created. Enhanced memory and storage technologies are being introduced. And the speed of the interfaces between them continues to increase.

Next-generation designs will be able to leverage all of these advances. For example, forthcoming storage and memory standards (like UFS and LPDDR) will support additional bandwidth and access to larger memories, further complementing the higher performance of nanosheet technology.

benefits-of-running-ai-models-on-mobile-edge-devices-infographic

Understanding the transition from FinFET to nanosheet technology

The last few generations of semiconductor technology have been based on FinFETs, three-dimensional field-effect transistors (FETs) marked by their thin vertical fins. However, the industry is now reaching the limit when it comes to shrinking FinFET technology.

The nanosheet transistor architecture is necessary to allow continued device scaling, reducing leakage while increasing chip performance and power efficiency. Currently, high-performance mobile SoC designs are leading the way in nanosheet adoption, with hyperscale servers and high-performance CPUs following closely behind. Nanosheet transistors ¡ª alongside new power distribution schemes and multi-die based designs ¡ª are poised to accelerate semiconductor innovation.

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Edge AI use case enabled by next-generation memory and storage standards

Synopsys IP: High performance with low power consumption

At Synopsys, we continue to invest in the most advanced process nodes to ensure our customers have the electronic design automation (EDA) and IP solutions they need to keep pace with the latest industry innovations. Our first-pass silicon success on 2nm nanosheet technology ¡ª for MIPI PHY and USB PHY IP ¡ª highlights our commitment to delivering nanosheet-ready IP.

We offer best-in-class interface IP and foundation IP solutions for TSMC's N2 and N2P processes, enabling high performance and low power consumption for advanced HPC, edge, and automotive chips. With successful deployment in thousands of designs, these IP solutions provide a low-risk path to first-pass silicon success.  

Paving the way for future chip design

We will continue , advance next-generation technologies, and leverage AI to revolutionize design processes.

Future chip designs will be more compact, faster, and increasingly energy efficient, serving as the foundation for highly integrated and advanced systems. These systems ¡ª and the silicon within ¡ª will define the era of pervasive intelligence.

Achieving this begins with proven IP solutions that are seamlessly integrated with cutting-edge process technologies.

 

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