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Escalating chip complexity and scale is an ever-present theme in any integrated circuit (IC) design discussion. The challenges are becoming especially acute as we move to the era of hyper-convergent ICs, which are not only larger and more complex, but also introduce new requirements to perform multi-dimensional verification of these highly integrated system-level chips.

Simply throwing more horsepower at the problem is no longer sufficient (although still needed). A more productivity-oriented workflow is essential to deal with the variety of verification challenges in a modern system-on-chip (SoC). Multiple verification methods need to work in concert, and overall productivity is just as important as individual tool performance. It calls for a revamped verification strategy. Call it a continuum.

So, What Exactly are Hyper-Convergent ICs?

The term SoC has been used for quite some time to describe an IC that contains multiple different types of components integrated onto a single die. Typically, the SoC is dominated by digital circuitry with smaller bits of analog, mixed-signal, IO, and memory integrated, but more likely located off-chip on the same printed circuit board (PCB). As computing requirements in sectors like data center, communications, and automotive have increased, and as IC manufacturing processes have evolved with new architectures and finer geometries, the single-chip platform has become more capable of containing a variety of embedded functions, from on-chip memory to high-speed IO.

Increasingly, multiple components are coming together in hyper-convergent designs to meet demands for bandwidth, performance, and power for these compute-intensive applications. Unlike the previous generation¡¯s mostly digital-centric SoCs, modern hyper-convergent ICs have integrated analog components, larger and faster embedded memory, and complex IOs with 100+ GB data rates. In a single package, there can be a variety of components, each responsible for different functions; some of these components will likely be on different process nodes and can be integrated on stacked die or 2.5D and 3D architectures.

That presents challenges both in terms of performance and capacity, as well as overall management of the verification process.

Performance and Accuracy for Today¡¯s Most Complex ICs

When you talk about verification of any type, speed is usually the first topic that comes to mind. PrimeSim Continuum delivers with industry-leading performance, anchored by two engines that enable unmatched throughput and capacity, alongside other integrated specialty simulation and analysis tools and productivity-enhancers.

Let¡¯s start with the new PrimeSim SPICE and get the speed argument addressed right up front: It¡¯s not only 3x faster than any other SPICE simulators, but it also introduces a unique performance scaling approach that enables heterogeneous compute acceleration using GPU architectures. All with no compromises in accuracy as it maintains golden signoff quality. Leveraging its unique hybrid CPU/GPU architecture, users can experience up to 10x performance scaling with golden accuracy for large post-layout designs.

Our customers acknowledge the importance of the performance benefits: ¡°As modern compute workloads evolve, the size and complexity of analog designs have moved beyond the capacity of traditional circuit simulators. Using NVIDIA GPUs enables PrimeSim SPICE to accelerate circuit simulation, notably minimizing signoff time of analog blocks from days to hours,¡± said Edward Lee, vice president of Mixed-Signal Design at NVIDIA, in a .

Because leading-edge manufacturing architectures such as FinFETS and processes at nodes scaling to 3nm introduce new challenges from a manufacturability and yield standpoint, a comprehensive analysis environment is needed. Issues such as electrothermal stress and larger parasitics must be addressed to focus on the chip reliability that manufacturing at scale will require. PrimeSim Continuum provides a complete set of analysis capabilities to consider time domain, frequency domain, and noise.

We¡¯ve also revved up our Fast SPICE engine to increase performance by up to 5x. A key advancement is our innovative partitioning and advanced modeling capabilities that help break down elements into manageable pieces to increase both runtime and overall capacity. The tool has proven to be capable of handling billions of elements that comprise a modern, complex 3D stacked memory design, for example, and still maintain signoff-quality accuracy.

PrimeSim Continuum includes a platform to integrate other tools from Synopsys¡¯ custom verification portfolio (including PrimeSim Pro, PrimeSim HSPICE, PrimeSim XA, and PrimeWave for advanced analysis) and is also integrated with Custom Compiler for accelerating analog design, VCS for mixed-signal verification, Verdi for interactive debug, and PrimeLib, our unified library characterization and validation tool.