Cloud native EDA tools & pre-optimized hardware platforms
The past year has raised the scope for innovation in chip design to a level unlike anything the industry has ever seen before. As the requirements from different industries and the chips that serve them become more complex, so does the design and verification process. The uptake of multi-die solutions has been considerable, and designers are becoming steadily more adept as they apply AI to their work. We have also witnessed the cloud feature more prominently to enable scale and flexibility, and lower costs.
Here is a look at the key developments in these areas and more that made 2023 such an exciting year in the electronics industry.
The move toward increasing intelligence in chip design has been ramping up, and 2023 saw some key milestones. In February, Synopsys Design Space Optimization AI (DSO.ai?), our award-winning autonomous design system, marked its . The technology has accelerated the development of advanced-node chips, raised productivity, and reduced die size resource consumption for customers such as STMicroelectronics and SK hynix.
Our AI journey continued in March 2023 with the launch of , the first full-stack AI-driven suite of electronic design automation (EDA) solutions to enable design, verification, testing, and manufacturing of the most advanced digital and analog chips. Qualcomm is one company using AI-driven verification to accelerate coverage closure, a story we told in August, while several major chipmakers expressed excitement about the potential for AI to dramatically enhance efficiency and chip performance while shrinking development timespans. As the year progressed, we continued enhancing Synopsys.ai, introducing Fab.da software that aims to make semiconductor manufacturing more efficient, amid shrinking chip sizes and a shortage of talent, with the ability to analyze petabytes of data. As a comprehensive process control solution, it uses AI and machine learning to enable faster production ramp and efficient high-volume manufacturing for advanced nodes.
Due to the ubiquity of AI this year (and the numerous performance needs that come along with it), we saw advanced multi-die systems answer these demands at an unprecedented level ¡ª and introduce a new, necessary level of design complexity. In March, a Synopsys-sponsored report by MIT Technology Review Insights (MITTRI) examined multi-die systems¡¯ pivotal role in semiconductor innovation.
At the center of multi-die advancement and standardization is the Universal Chiplet Interconnect Express (UCIe) standard for die-to-die connectivity. Applying this standard ensures interoperability, minimizes latency, and enables repairs to be conducted through redundant lanes. This, together with high-quality dies, IP, emulation and verification tools, and ongoing testing, will serve as the foundation for multi-die system evolution.
In addition to the benefits multi-die systems bring to the table, the advent of AI chips calls for additional new chip architectures ¡ª both software and hardware that are optimized for efficiency. We expect to see accelerated adoption of next-generation process nodes to enable performance gains; experimentation with different types of memory, processor technologies, and software components; and increased use of photonics as well as multi-die systems to overcome AI chip bottlenecks.
Just as AI is changing the way chip designs look, it is also having a profound impact on the way designers work, helping them achieve higher levels of productivity and better outcomes. As we noted in July, designers are raising the bar in terms of possibility and quality every few months. Impressive as this has been, it will become harder as everything shrinks. STMicroelectronics and Microsoft offered two examples of how AI has helped designers multiply productivity by up to 3x and reduce power dissipation by 15%. To further enhance engineering productivity, we launched Synopsys.ai Copilot in November, bringing a generative AI-based smart assistant to our EDA flow.
Another example of enabling productivity in the EDA space is our collaboration with AMD to launch 4th Gen AMD EPYC? processors with AMD 3D V-Cache? technology. Whether designers are developing monolithic SoCs or multi-die systems for high-performance computing (HPC) applications, the accelerated processing speed helps them get their products to market faster.
Beyond the design desk, we saw how deep-learning models are driving advances in computer vision, integral for autonomous driving and increasingly prevalent in mobile phones, security systems, and digital personal assistants. We are also starting to see the coexistence of convolutional neural networks (CNNs) and transformers, which use deep learning to process all input data at once, leading to more accurate vision processing applications.
In addition to harnessing AI, the cloud has become another vital tool for many industries due its flexibility and scalability. EDA tools and chip design workloads continue to migrate to the cloud, given ever-increasing compute demands, accelerated time-to-market requirements, evolving cyberthreats, and the need for flexible, cost-effective storage.
That¡¯s why we unveiled Synopsys Cloud 4.0 in July to deliver e-commerce and Synopsys ZeBu? cloud software-as-a-service (SaaS) flows with scalable, unlimited compute capacity. While the technology at work is complex, the goal is simple: to help semiconductor companies drive innovation and design high-performing chips faster. The 4.0 release features the latest SaaS instance, bringing silicon photonics to a lineup that includes analog, digital, and verification SaaS instances for accelerated time to market. And in November, we introduced the Synopsys Cloud OpenLink program, which supports seamless interoperability for multi-vendor flows on Synopsys Cloud, giving designers new levels of design freedom.
AI accelerators are critical for automated information delivery in areas such as e-commerce, autonomous driving, and online video gaming. The PCI Express? (PCIe?) high-speed interface enables this by ensuring that data can travel between the accelerator and the host (CPUs and GPUs) with little latency. In September, we looked at how PCIe supports this while doubling bandwidth with each new generation, with a focus on the latest iteration, PCIe 6.0. Separately, we looked at how AI accelerators are evolving in data centers and at the edge as Moore¡¯s law slows to enable the technology we rely on, ranging from advanced driver assistance systems to smart edge devices such as cameras and sensors.
Another launch in the interest of addressing complexity was that of the , the industry¡¯s first emulation system to support electronic digital twins of advanced SoCs. The server offers 1.6 times more capacity than its predecessor and twice the throughput and emulation performance at less than half the power consumption.
As an industry, we are always stronger together. Indeed, we see collaboration as our most advanced tool. The designing of multi-die systems is one rapidly evolving area where we see collaboration hastening adoption. Our partnership with Samsung Foundry led to the development of Samsung Foundry¡¯s Multi-Die System Implementation Flow with Synopsys 3DIC Compiler, supporting Samsung process nodes and I-Cube? and X-Cube? technologies. Working together, we are helping design teams achieve their PPA goals with multi-die systems to rise to the challenge of complex applications such as AI, HPC, and automotive.
A collaboration with Ansys, Keysight Technologies, and TSMC saw the development of a radio frequency (RF) design reference flow for the TSMC 16 nm FinFET Compact Technology (16FFC). As an enabler of ICs for autonomous systems such as automotive radar, we are one step closer toward realizing ambitious autonomous driving dreams.
Further initiatives with TSMC included the to enable faster delivery and higher quality of advanced-node SoCs and the launch of the industry¡¯s broadest portfolio of for TSMC¡¯s N5A process.
We also around the unveiling of Arm? Total Compute 91³Ô¹ÏÍø 2023 (TCS23) at Computex. Synopsys system-level solutions for the platform include Synopsys.ai, Synopsys Interface and Security IP, and Synopsys Silicon Lifecycle Management PVT IP. These advancements build on decades of collaboration between the two companies to accelerate delivery of high-performance, efficient Arm-based SoCs for high-end smartphones and virtual reality applications.
At Synopsys, we always have at least one foot in the future. We envision the future as smart ¡ª befitting of a world that requires resourceful problem-solving. Speaking at SNUG Silicon Valley in April, Synopsys Chair and CEO Aart de Geus framed chip design as a highly creative undertaking. ¡°We¡¯re working on artwork, and the art of changing the world,¡± de Geus said. ¡°In that context, we catalyze the future. We work together on problems that are unbounded.¡±
Working toward the goal of a smart future underpins all our actions, including our environmental, social, and governance (ESG) strategy. In May, we detailed our progress, from our fourth consecutive year achieving CarbonNeutral certification to our millions in charitable donations.
Another forward-looking initiative this year was a new returnship program designed to address the issue of career breaks for the caretaking of children, elderly parents, or a sick spouse. The Synopsys Reignite Your Aspiration (RIYA) Returnship program offers new career opportunities to people with experience in electrical, software, and computer engineering and computer science, among other areas. We also remain committed to building a diverse workforce and our burgeoning employee resource groups play a key role in encouraging inclusion. To mark Pride month in June, we interviewed several of our LGBTQIA+ engineers as part of the activities of the Synopsys Pride ERG.
At the other end of the talent spectrum, we recognize the importance of contributing to a strong pipeline of future workers by fostering STEM education through the Synopsys Academic and Research Alliances (SARA) program. In a related highlight, one of our engineers, Ron Duncan, appeared in the Roadtrip Nation documentary series, which encourages students to channel their personal interests into fulfilling careers.
To facilitate training in the post-classroom, decentralized work era, we launched the Synopsys Learning Center. Registered Synopsys users can use this online hub to get up to speed on Synopsys products in the way that best suits them with an on-demand subscription model that delivers a personalized learning experience.
While 2023 saw some remarkable EDA and IP achievements, 2024 promises to kick off a new era. As of January 1, 2024, Sassine Ghazi will become president and CEO, with Aart de Geus taking on the role of executive chair. Ghazi has spent 25 years at Synopsys and embodies our ¡°Yes, if ¡¡± philosophy.
¡°As I step into the role of CEO, I am fueled by an unwavering determination to build upon our strong foundation, drive innovation, and propel Synopsys to even greater heights of success,¡± Ghazi said.
Other major appointments from 2023 that lay the foundation for an exciting 2024 included that of and . In an interview, our CFO Shelagh Glaser shared a helpful perspective on breaking the glass ceiling: ¡°Traditionally, women are coached on leadership behavior and not on the business. I don¡¯t care how straight you sit at the table. The people that get ahead in life are people that change and drive business impact. Be that person.¡±
Embracing change is part of our cultural makeup. As ever, uncertainty abounds in the world but so does opportunity. We are looking forward to a highly stimulating 2024 and wish you and your loved ones the very best.