91³Ô¹ÏÍø

The Rise of RISC-V Processors

RISC-V¡¯s flexibility comes from its unique set of features that enable users to optimize both software and hardware for specific use cases, ideally improving both performance and energy efficiency.

Beyond flexibility, RISC-V offers developers and designers greater control over their computing environments and allows them to fine-tune the system without relying on third parties. As an open-standard platform, RISC-V also allows users to avoid the license fees otherwise associated with proprietary architectures.

Finally, a third benefit for developers is added visibility into the code base, its evolution, and potential security risks.

Then, there is the field of Internet of Things (IoT). Here, devices spend most of their time in sleep mode, intermittently coming to life to process and send information. This field also requires a long battery life.

On the flip side, power can become a constraint in that it sets thermal limits and becomes a reliability issue, leading companies to find ways to optimize performance per watt. In this context, reducing power becomes the basis for increasing performance and pushing the power-performance envelope.

Addressing RISC-V Power Efficiency Challenges with Early Power Analysis

The flexible nature of RISC-V is a valuable asset in terms of the customization potential it affords developers. But it also poses questions around the implementation of a software algorithm. Will it be general-purpose, hardware-instruction set architecture? Or are there benefits to be had from adding or extending the instruction set architecture with new instructions? Such decisions determine how efficiently the algorithm will run from both a performance and energy efficiency standpoint.

Of course, there is no such thing as a free lunch. Extending the instruction set architecture might enhance performance and energy efficiency. But the upshot is also a more complex processor. Implementing new instructions translates to logic gates and the penalty of additional design area usage. There is an inevitable trade-off between power, performance, and area (PPA), and a developer or designer making these choices must be clear on what it is and on what the function of the process is going to be. 

But how can the designer assess these PPA trade-offs?

Once the design architecture is defined as RTL, power analysis tools such as PrimePower RTL can be used to assess the power consumption of the design early in the process. PrimePower RTL delivers consistent accuracy as compared to the final power signoff results, allowing the user to make informed, confident decisions to optimize their design. 

The other crucial component for this process is emulation. With the Synopsys ZeBu? emulation system and ZeBu Empower ¨C a massively parallel power analysis tool ¨C power analysis is performed with a realistic workload, avoiding the pitfalls associated with synthetic simulation vectors that don¡¯t represent real-world use cases. With the aid of these Synopsys tools, the designer can explore the PPA trade-off and, after running analysis on different architectures for comparison, choose the most appropriate one for the task at hand.

It bears emphasizing that RTL is a technology-independent language that requires physical implementation, which is the role of the Synopsys Fusion Compiler? solution. Fusion Compiler is a hyper convergent implementation solution where unified RTL-to-GDSII optimization engines unlock new opportunities to identify the best performance, power, and area. When used in conjunction with?Synopsys DSO.ai?, it becomes possible to streamline the process to produce lower-power, higher-performance, smaller-area designs automatically within a compressed timeframe.