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A familiar friend is making a mark on the RISC-V landscape in a new and impactful way. Synopsys has expanded its ARC? processor IP portfolio with a new RISC-V-compatible family. While the next-generation Synopsys ARC-V? processors mark our first foray into processor IP based on the open-standard RISC-V instruction set architecture (ISA), we¡¯ve long played a key role in delivering configurable and extensible processor IP to SoC designers.

Our existing ARC processors will continue to be in the mix as we roll out the new ARC-V ISA for future generations of our cores. The first of our ARC-V embedded cores, co-optimized with Synopsys.ai? full-stack AI-driven EDA suite and our leading verification solutions, will be available during the second quarter of 2024. These processors are ideally suited for a variety of power-critical applications in automotive, storage, and artificial intelligence of things (AIoT) designs. Chip designers will gain a broader range of flexible, extensible processors from a provider with a decades-long track record for delivering and supporting PPA-efficient implementations and optimized software development tools and libraries.

Synopsys has been a familiar presence in the RISC-V ecosystem for some time now as a member of RISC-V International, the global nonprofit that manages the standard. We recently joined the organization¡¯s board of directors and its technical steering committee. Read on for more details about our new ARC-V processors, and how we can help chip designers optimize and differentiate their RISC-V processor-based SoCs for a wide range of applications. 

Strengthened by a Broad and Expanding Ecosystem

Synopsys provides a broad array of solutions to support and streamline the development of RISC-V-based ARC-V processors. The Synopsys ARC MetaWare Development Toolkit, which includes all the components needed for developing, debugging, and tuning software applications, has been optimized for ARC-V processors. The ARC MetaWare Development Toolkit for Safety helps accelerate development of ISO 26262-compliant code for safety critical use cases. In addition to our own tools and operating systems, Synopsys also maintains an ecosystem of embedded hardware and software partners who provide development solutions for ARC processor-based systems across a wide array of market segments. The Synopsys electronic design automation (EDA) portfolio supports ARC-V based SoC architecture exploration, design, implementation, verification, and silicon lifecycle management, and can also be leveraged in any RISC-V based development. Synopsys IP can be easily integrated into any ARC-V based SoC.

For designers who opt to build their own RISC-V implementations, Synopsys ASIP Designer? tool suite will continue to provide an option that automates design of custom RISC-V processors and accelerators, from architecture exploration through RTL generation.  The Synopsys software integrity portfolio helps to manage the security, quality, and license compliance risks that can come with using open-source and third-party code in applications and containers. And Synopsys Cloud native EDA tools and pre-optimized hardware platforms help enhance design productivity, as well as performance, turnaround time, and accuracy.

As design teams seek new ways to differentiate their SoCs, the RISC-V ISA provides a pathway for standardization and shared investment so chip developers can focus on their unique value add.  Synopsys¡¯ new ARC-V processor IP, combining the expanding RISC-V ecosystem and Synopsys¡¯ extensive experience in processor IP, provides a reliable option designers can trust to take their customized SoCs to new competitive heights.