Cloud native EDA tools & pre-optimized hardware platforms
Advancements in memory technology are fueling rapid growth in big data applications across AI, 5G, Automotive, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated, while the latest technology nodes have introduced some new ones. At Synopsys, there is a corporate-wide commitment to developing broad-based solutions that address these challenges.
Memory vendors are accelerating the shift to next-generation HBM and new memory architectures to cater to the insatiable demand for high bandwidth, high performance memories driven by AI applications.
These next-generation designs pose many challenges for memory designers. Some long-standing challenges have been exacerbated, and some new ones have been introduced.
The Synopsys Memory Users Conference aims to provide a forum for memory companies and Synopsys experts to share their perspectives on ways to address the industry¡¯s most compelling and topical challenges. Drop in to learn more!
Learn more about the themes we will explore during this virtual event. More information around sessions are being confirmed daily, so be sure to check back often for new information.
08:00 AM - Welcome Introduction
Anand Thiruvengadam, Senior Director of Product Management, Product Management & Markets Group, Synopsys
08:01 AM - Synopsys Keynote: Memory Innovations in the AI Era
Shankar Krishnamoorthy, GM, Synopsys
08:20 AM - Industry Keynote: Memory Trends in the Golden Age of AI
Chris Collins, SVP of DRAM & Emerging Memory Engineering, Micron
08:35 AM - NAND Flash Scaling and TCAD Application
Yan Li, Western Digital
09:05 AM - Custom Circuit simulation at Digital speed! Accelerating Fast SPICE Simulation in Flash Memory using PrimeSim Hybrid Timing
Yusuke Ono, Kioxia
09:30 AM - Accelerating Circuit Simulation using GPU
Veerabhadra Rao Boda, Nvidia
09:45 AM - High Verification Coverage with ESP in Full custom SRAM Memory Design
Anukriti Singh, STMicroelectronics
10:05 AM - Hyperconvergence of Static-Aware Synthesis Solution for Samsung Memory
Jeonghun Heo, Samsung and Rimpy Chugh, Synopsys
10:30 AM - The Path to Emerging NVMs goes through Co-Simulation with Synopsys
Ilan Sever, Weebit Nano
10:50 AM - Ensuring Quality, Safety & Reliability for Today¡¯s Emerging Memories
Yervant Zorian, Synopsys
11:15 AM - Improving Design Robustness and Testability of CAMs in High Performance Network Switch Processors with Synopsys SLM SMS Technology
Vinay Kumar, Intel
11:35 AM - Industry Panel: Optimizing Memory in Multi-Die Architectures
Moderator: William Wong, Senior Content Director at Electronic Design
Panelists: Huijuan Wang, Western Digital; Raghu Sreeramaneni, Micron; Murat Becer, Ansys; Sutirtha Kabir, Synopsys.
Shankar Krishnamoorthy
General Manager
Synopsys
Memory Innovations in the AI Era
Rapid advancements in memory innovations are being driven by the emerging AI era. This presentation will explain how semiconductor demand, accelerated by pervasive intelligence, is set to push industry revenue beyond a trillion dollars within a decade. Key drivers include AI build-out at data centers and the edge, silicon proliferation, and increased software content, which will necessitate new memory architectures to meet AI's computational demands. Finally, the presentation will describe how Synopsys' investments in comprehensive EDA and IP solutions enable designers and system architects to overcome challenges in memory performance, design complexity, and thermal stress, enabling memory technology transformations that are critical to the AI era.
Chris Collins
SVP, DRAM & Emerging Memory Engineering
Micron
Memory Trends in the Golden Age of AI
With breakthroughs in compute and memory subsystems, innovative software algorithms, massive data sets, and ubiquitous connectivity colliding, we are entering the Golden Age of AI. This is creating megatrends in the memory space that are driving simultaneous innovations in power, speed, and capacity. High Bandwidth Memory (HBM) is at the forefront enabling massive data set usage for generative AI as well as in the automotive space. With memory consuming more than 30% of the power of an AI system, this talk addresses some of the challenges facing compute systems in this Golden Age of AI.
Dr. Yan Li
VP of Advanced Technology
Western Digital
NAND Flash Scaling and TCAD Application
NAND flash memory has numerous applications, from mobile phones to data centers. It also has been widely adopted in Solid State Drives (SSD) over the last 10 years. NAND scaling has continued rapidly into the current 3D NAND era where not only are the number of layers growing rapidly, from 32L in 2017 to 300L in 2024, but also the memory is compacting in other dimensions. Currently NAND capacity in a single SSD drive can be as high as 128TB and will soon be increasing to 1PB.
There are challenges faced due to the continued aggressive physical scaling in the 3D NAND era. Capital expense (CapEx) has increased dramatically from one generation to the next due to the complexity of stacking 3D cells vertically. The growth in the total amount of capacity from 3D NAND products has flooded the markets with a lot of bits, and therefore has driven down the price of flash products. This benefited many applications but caused difficulties for NAND manufacturers. The new 8th generation chips from WDC are a new generation providing improved technology with good cost reduction and high performance by using CMOS Bonded Array (CBA) technology. The application of TCAD tools in 3D process technology helped WDC design these complicated structures efficiently and economically.
Yusuke Ono
Design Technology Specialist
Kioxia
Custom Circuit simulation at Digital speed! Accelerating Fast SPICE Simulation in Flash Memory using PrimeSim Hybrid Timing
NAND Flash memory design involves many iterations to meet the stringent demands for functionality and performance. These design iterations trigger verification cycles for logic and custom designed circuitry. The custom designed circuits require SPICE-level simulations and are time consuming due to the large number of analysis vectors, whereas the logic circuits are easily verified with fast digital simulation methods. To alleviate this custom design verification challenge, we applied an innovative technology in PrimeSim called Hybrid Timing and have achieved significant performance improvement. In this session, we will share our findings and some tips on usage.
Veerabhadra Rao Boda
Engineering Manager
Nvidia
Accelerating Circuit Simulation using GPU
This presentation explores the utilization of GPU acceleration to enhance the speed and efficiency of fast spice circuit simulation. Traditional CPU based circuit simulation encounter computational bottle necks particularly on large custom memories with PDN (Power Delivery Network) and hindering design iterations. Timing needs to be very accurate at lower geometry nodes with PDN and any inaccuracy can result in silicon bugs. To circumvent silicon bugs, excessive padded margins are adopted, resulting in a compromised performance. PrimeSim simulator from Synopsys with GPU computing support enable the accurate timing analysis with PDN from 19days to 4days (5x improvement). This presentation aims to bring out various details and facets of GPU based sims in a qualitative and quantitative means.
Anukriti Singh
SRAM Memory Circuit Designer
STMicroelectronics
High Verification Coverage with ESP in Full custom SRAM Memory Design
Over 50 percent of the total silicon real estate in today¡¯s SoC is consumed by memories. And as designs move toward sub-nanometer process technology, functionalities such as redundancy, ECC, BIST, pipelining, etc. are being added to these designs, resulting in significantly higher functional complexity.
ESP is an equivalence checking tool commonly used for functional verification of custom designs such as embedded memories, standard cells , Io¡¯s etc. It compares transistor-level SPICE netlist with the reference Verilog. It is used to cover various possible combinations of cases to test memory functionality & could also ensure first level of design sanctity. E.g. ESP uses formal techniques to quickly verify that the redundancy logic added to the memory array to replace defective cells and improve yields is performing correctly. In this presentation we will be sharing functional verification of SRAM memory in various modes. Also, ways to debug the errors & generate waveform when failure doesn¡¯t exist.
Jeonghun Heo
Staff Engineer
Samsung Electronics
Hyperconvergence of Static-Aware Synthesis Solution for Samsung Memory
This presentation will introduce CDC verification and power saving related technologies from RTL to netlist. CDC verification is performed in RTL generally, sign-off for CDC is performed through VC Spyglass. Once CDC verification of RTL, need to check for CDC problems that may occur due to the converted netlist. Typically, CDC analysis is difficult to manage at netlist. We can automate CDC verification by applying the RTL CDC verification results to the netlist through hyperconvergence. In addition, Power can be saved through the "Unexpected Self Clock-Gate Control" technology of hyperconvergence.
Ilan Sever
VP R&D
Weebit Nano
The Path to Emerging NVMs goes through Co-Simulation with Synopsys
Performance demands of emerging applications are driving the industry to look for new memory technologies and architectures. In this talk we will introduce Weebit ReRAM, an emerging non-volatile memory (NVM) technology with unique advantages for SoC designs across applications from IoT and MCUs to edge AI and automotive to future neuromorphic computing use cases. With ReRAM, a combination of precision analog and smart algorithms is key to achieving high performance. This presents unique verification requirements that make co-simulation a must-have tool before tapeout. We will discuss how using Synopsys verification tools for co-simulation can lead to a significantly higher level of confidence than traditional methods.
Yervant Zorian
Synopsys Fellow
Synopsys
Ensuring Quality, Safety & Reliability for Today¡¯s Emerging Memories
Today¡¯s advanced applications in HPC, AI and automotive require the adoption emerging memory technologies, including off-chip memories, such as HBM and DDR stack in chiplets based 3DICs, and embedded specialty memories such as CAMs & MRAMs. This presentation will address today¡¯s trends and discuss the quality, safety and reliability challenges of these emerging memories throughout their different lifecycle stages. It will focus on optimizing the health of such emerging memories by managing their silicon lifecycle stages: from early-stage characterization and bring up; to volume production BIST and repair, and all the way to in-field power on self-test & repair, periodic in-system checking and finally to fault tolerance and error correction during real-time mission mode. These optimizations for quality, safety and reliability are realized by using advanced SLM IP types augmented by off-chip data analytics.
Vinay Kumar
Technical Lead
Intel
Improving Design Robustness and Testability of CAMs in High Performance Network Switch Processors with Synopsys SLM SMS Technology
Content-addressable-memories (CAMs) are commonly used in high-performance network switch processors for supporting faster table look-up operations. CAMs require testing (and repair) of the storage aspect of regular memory bit cells as well as comparing data cells. It also requires testing (and repair) of the compare logic which is observed via match output data. Match output data width is equal to the depth of the CAM without encoding. Match data width can be reduced to log2(N) through binary one-hot or priority encoding, but it limits the functional usage of CAM to observe only one match at a given instance of time. Hence, complete access to match data would require the match output without encoding to be available for observability by downstream functionality. In this scenario, routing the match output data from multiple CAMs to the memory BIST processor leads to routing congestion issues. In the case of networking SoCs, that rely on intensive usage of CAMs, the parallel match data routing resource challenge, makes physical implementation of the memory BIST solution infeasible. This paper proposes a novel memory BIST architecture for CAMs that makes physical implementation of the memory BIST solution feasible by reducing the match data routing resource requirements while maintaining full testability and repairability of compare logic. This solution adds minimal area overhead, with no impact on functional path timing closure. This solution has no additional test time impact either. Hence this novel approach can enable a physical implementation-friendly CAM memory BIST solution for an exhaustive test (and repair), especially for SoCs that have extensive usage of CAMs, like networking switch processors. With SLM (Silicon Lifecycle Monitoring) CAMs will be accessed for in-field testing and diagnosis support.
Optimizing Memory in Multi-Die Architectures
Multi-die designs have emerged as the next big disruption in computing to cater to the unsatiable need for larger, faster, and more energy efficient compute systems. For such high-performance computing systems there is a need for memories to perform at peak levels, while optimizing power, performance, area, and cost. Attend this panel to get insights into the different memory chip design and verification approaches for multi-die designs. Don¡¯t miss out on hearing what industry experts have to say about the use of HBM and other memory technologies in 2.5 and 3D packaging.
William Wong
Senior Content Director
Electronic Design
Huijuan Wang
Sr. Director VLSI Design Engineering
Western Digital
Raghu Sreeramaneni
Director of HBM Architecture
Micron
Murat Becer
VP of Product
Ansys
Sutirtha Kabir
R&D Engineering Sr Director
Synopsys