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RISC-V is reshaping the tech industry as more companies choose to leverage the customizability, scalability and flexibility offered by the RISC-V ISA and ecosystem. RISC-V provides opportunities for innovation, giving SoC architects and software developers the ability to define new products and create a high degree of differentiation in their product portfolios. However, successful development of RISC-V based SoCs requires expertise in digital design, verification, and embedded systems, along with proven EDA, verification and software development tools. Learn how Synopsys¡¯ comprehensive, ready-to-use design, verification, and ARC-V?  processor IP solutions enable designers to achieve their IC design goals and accelerate time to market for their RISC-V based SoC.

Developing a RISC-V based SoC, both hardware and software, requires a range of expertise and use of best known methods and technologies.? Synopsys provides solutions from the beginning of the project, architecting the SoC, through implementation including RISC-V processor IP and verification of self-built RISC-V processors, through to software development on the SoC.?

Functional models of RISC-V processors are critical to the success of RISC-V projects, whether users are developing the processors themselves or licensing the processor IP.  These models enable architectural exploration at the beginning of the project, including the addition and optimization of custom instructions, provide a reference model for design verification of the processor, and provide a high performance, instruction accurate model for virtual prototypes used for software development.  Key requirements for these models are ease of use, flexible configuration, including adding custom instructions, CSRs, etc., and high performance of the models.  This paper discusses the use of the open standard used in C/C++ for building high performance processor models. 

By having a robust set of APIs, which have been developed to support multiple processor architectures including Arm, MIPS and more, it becomes much easier to build new models and maintain existing models.  This high-performance model architecture and APIs have been proven over 15 years, 16 architectures and 300+ specific processor models.  The ImperasFPM fast processor models, developed using the OVP APIs, support all the use cases, including interfacing to various 3^rd party tools, such as SystemVerilog and SystemC simulators, hardware emulators and FPGA prototypes.