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The automotive industry is undergoing a significant transformation. Cars are offering increased connectivity and capabilities to provide a better driver/passenger experience. The increased connectivity means that they are also collecting and transmitting more sensitive data between in-car systems and the cloud, and thus are becoming very attractive targets to hackers. Security must be addressed from the ground up starting with the SoC, and when applied to cars, security needs to be approached together with automotive safety in a holistic manner. Designing security into automotive SoCs from the hardware level with safe and secure Hardware Secure Module (HSM) IP with a root of trust will help ensure that connected cars behave as expected, prevent random and systematic faults, and are able to fend off malicious attacks. Join this session to learn how the tRoot HSM for Automotive and ARC SEM130FS Processor implement the critical security and safety functions required throughout the automotive SoC life cycle.

With shorter development cycles, software complexity and safety & security requirements facing the automotive industry, challenges exist to deliver system components to OEMs or Tier 1s to meet start of production (SOP) dates and provide updates or new features after SOP. AUTOSAR is the key to a centralized ECU architecture for mass production ready system components that are safe, secure and flexible. In this presentation we will map out vehicle and ECU architecture (including the Synopsys ARC Functional Safety Processor), benefits for both Classic and Adaptive AUTOSAR development and define best use case scenarios.

Robust and timely perception of the environment is an essential requirement of all autonomous and semi-autonomous systems. This necessity has been the main factor behind the rapid growth and adoption of LiDAR sensors within the ADAS sensor suite. This presentation will describe a new, fast and accurate 3D object detector, FA3D, that converts raw point clouds collected by LiDARs into sparse occupancy cuboids to detect cars and other road agents using a deep convolutional neural network. This highly flexible mode uses an efficient input encoding representation that is multiple times faster to compute on a CPU and more compact to transfer to a GPU, without increasing power. As a result, FA3D reduces by almost 50% the detection runtime compared to popular 3D detection networks and performs on par with other state-of-the-art models. The performance results of this network will be demonstrated for the case of vehicle and vulnerable road user detection. The presentation will also compare the performance of this model on three off-the-shelf neural network accelerators: 1) a high-end workstation equipped with a Core-i7 CPU and a RTX 2080 Ti graphics card, 2) a Jetson AGX Xavier (a single board embedded computer with an 8-core ARM processor and 512-core Volta GPU), and 3) Synopsys DesignWare EV Vision Processor IP core with a highly optimized CNN engine.

Artificial Intelligence continues to find ways to improve the world around us. Working with their partner Alps Alpine, Inuitive discusses how they applied expertise in system design, computer vision and deep Learning/AI to make electric carts safer. This talk will discuss the challenges in the design including overcoming environmental, safety, performance and cost issues. Also discussed will be the need and process for retraining off the shelf neural networks and how combining depth sensing with neural networks can provide the optimum solution.

With the evolution of edge computing, edge devices are handling more data processing at the source instead of sending it to the cloud. The edge devices are distributed and decentralized, enabling them to perform necessary computations on-device rather than outsourcing it to the cloud. These devices report results into aggregators and eventually into a centralized compute resource on the premises or cloud. This heterogeneous architecture offers some data security advantages but also brings increased risks in access security. Join this session with SiMa.ai to learn how SiMa.ai is addressing security risks at the edge by providing comprehensive solutions within its leading MLSoC? platform including the root of trust, secure boot, and runtime authentication to address diverse customer needs. SiMa.ai will also describe their driving factors for integrating security IP for target applications such as automotive, autonomous, robotics and computer vision.

NB-IoT technology has been designed to significantly reduce the power consumption of communication devices and improve spectrum efficiency. Demand for greater design complexity and extended coverage for ultra-low power IoT applications has driven a worldwide proliferation in wireless technology with NB-IoT protocol support. This presentation highlights the key challenges and requirements of today¡¯s NB-IoT modem designs and gives an overview of the Synopsys DesignWare ARC IoT Communications IP Subsystem, which leverages the efficiency and extensibility of the ARC EM11D processor with integrated, pre-verified hardware and software IP to help shorten the time-to-market for developing IoT communication products.

A typical SoC has multiple processors to offload the main CPU and achieve the required bandwidth for data intensive end-to-end operations. Verification of these SoCs requires compiling C code and loading this compiled code into the processor, after which the CPU starts executing these instructions and initiates a series of read/write operations on the system bus. Since processors are mostly pre-verified, the verification at the SoC level is mostly targeted to check interactions among multiple peripherals and memories. A datapath scenario is time consuming because of the large number of memory read, write and compare operations and reproducing a failure might cause a lot of rerun time due to long running memory accesses. To overcome this issue, most of the SoC level environment performs backdoor operations on memory access but this requires modifications in the C tests along with handshaking with the SV/UVM testbench. The same C test cannot be run on FPGA/emulation platforms due to backdoor dependencies, which creates issues with reusability of C tests on these platforms. In this presentation, we will describe how integrating the Synopsys ARC nSIM instruction set simulator in our simulation environment reduced simulation runtime by more than 5x.

The growing dependency of modern automobiles on electronic functions increases the need for many kinds of integrated circuits (IC) for safety critical applications. Requirements coming from different in-car subsystems mandate chip manufactures to create a wide range of specialized solutions. This in turn raises the bar for automotive IP suppliers and pushes them to offer configurable and extensible IP products. When IP configurability meets safety standards, it brings new technical challenges. Dual core lock step (DCLS), which is now the dominating safety mechanism for processing units, cannot work anymore as a one-fits-all approach. Increasing complexity of automotive grade ICs requires non-DCLS solutions. This trend brings new safety mechanisms into play. Software based self-test is one of those which has started to see increased demand. This presentation introduces Software Test Libraries (or STL) and explains how a holistic safety approach to hardware design can help to create an optimal combination of hardware and software safety mechanisms, demonstrating the best possible power, performance, area hardware metrics and minimal runtime software overheads.

With the rapid shift to ADAS and autonomous driving, carmakers are transitioning to a more centralized domain architecture with central compute. The system-on-chip (SoC) manages every aspect of its domain while at the same time ensuring safe and secure operation. Complex automotive SoCs require automotive-grade IP and ISO 26262-certified safety-aware test, design implementation, and verification solutions for hardware and software elements of the SoC to meet the strictest functional safety objectives while achieving power-performance-area (PPA) targets. This session provides an overview of automotive trends, describes Synopsys¡¯ safety-aware solution to enable and accelerate ASIL-compliant SoC designs, and delivers a video demonstration of an ARC HS46FS processor IP analyzed, implemented and verified using Synopsys¡¯ safety-aware solution to achieve ASIL D random hardware metrics.

Building ASIL D Compliant SoCs with Synopsys¡¯ Safety-Aware Solution & ARC FS Processor IP ¨C Synopsys

With the global manufacturing chip constraints, first-time-right silicon has never been more important. Automotive SoC developers need first silicon to meet stringent ISO 26262 standards as well as power, performance and area targets. In this demo, we will showcase Synopsys¡¯ Safety-Aware Solution, which includes tools and technology to reduce the risk of human error, accelerate the design cycle, and improve overall QoR. The Safety-Aware Solution for Random Hardware Faults allows designers to implement and verify functional safety mechanisms to address their ISO 26262 requirements. The demo uses ARC HS46FS Processor IP, showing how integrating ASIL D compliant processors simplifies the development of high-performance safety-critical applications to meet ISO 26262 certification.

Combining SLAM and Object Detection with DesignWare ARC EV Processor IP ¨C Synopsys

Autonomous vehicles, robotics, augmented and virtual reality all require simultaneous localization and mapping (SLAM) to build a map of the surroundings. Combining SLAM with a neural network engine adds intelligence, allowing the system to identify objects and make decisions. In this demo, Synopsys ARC EV processor¡¯s vision engine (VPU) accelerates KudanSLAM algorithms by up to 40% while running object detection on its CNN engine.

Fast & Accurate 3D Object Detection for LiDAR with DesignWare ARC EV Embedded Vision Processor IP ¨C Synopsys

LiDAR is widely used in automotive ADAS applications because it can detect obstacles and the distance to each one. LiDAR processing has been traditionally done by DSPs, but now companies are applying the latest deep learning techniques to LiDAR object detection. This demo, developed in partnership with Sensor Cortek, executes the FA3D algorithm on the ARC EV7x processor with DNN engine. The demo shows 3D boxes rendered onto objects detected in the video frames, enabling the development of safe and secure driver assistance systems.

Low-Power Machine Learning Inference with DesignWare ARC EM9D Processor IP ¨C Synopsys

This demo highlights building a CNN based application to recognize hand-written characters leveraging a Synopsys ARC EM processor and the embARC MLI library. Characters drawn on the screen will be passed to an EMNIST based neural network, which recognizes and displays the character on the screen along with the confidence value.

Moving Natural Language Processing to the Edge with DesignWare ARC VPX Processor IP ¨CSynopsys

Smart speakers and voice-controlled devices are getting better at understanding our requests through natural language processing (NLP). Current NLP implementations handle the applications¡¯ complex processing needs by sending requests to the cloud. To address the potential latency that is inherent in cloud processing, designers are integrating on-chip embedded processors to perform complex processing locally. This demonstration shows how Synopsys DesignWare? ARC? VPX DSP Processor IP can help move natural language processing from the cloud to embedded edge devices for lower latency with excellent power efficiency. ARC VPX DSP Processor IP is built on an advanced VLIW/SIMD architecture and optimized for high performance with low power consumption for always-on AI edge devices.

Real-time Trace: A Better Way to Debug Embedded Applications ¨C Ashling

Ashling¡¯s Ultra-XD is a high-performance real-time trace probe for embedded development and debug on Synopsys¡¯ DesignWare ARC EM and HS processors. Developed in cooperation with Synopsys, the Ultra-XD probe integrates with the MetaWare Debugger and IDE (MDB and MIDE) under Windows or Linux based hosts. In this demo, Hugh O¡¯Keeffe, Ashling VP of Global Engineering will show operation of the Ultra-XD with the Synopsys AXS103 Hardware Platform.

TASKING Tools for ARC Safety Critical Software ¨C TASKING

See a demonstration of the upcoming TASKING SmartCode development environment supporting Synopsys ARC in automotive safety critical applications. This toolset contains dedicated C/C++ compilers and assemblers, a multi-core linker/locator and debugger all within a unified Eclipse? Integrated Development Environment (IDE).

Vibrant Super Resolution (SR-GAN) with DesignWare ARC EV Processor IP ¨C Synopsys

Super resolution constructs high-res images from low-res. Neural networks like SR-GAN can generate missing data to achieve impressive results. This demo shows SR-GAN running on ARC EV processor IP from Synopsys to generate beautiful images.