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Join us in-person on September 25th for the annual Synopsys VC Formal Special Interest Group (SIG) event. This event provides an opportunity for users, managers, and enthusiasts to stay connected with the latest formal verification innovations, techniques and methodologies. Attendees will hear about groundbreaking and successful applications and deployments of Synopsys VC Formal including next-gen technologies that enable broader applications of formal verification and deeper analysis to get more proof and find more bugs in the design. This year¡¯s invite only event will include presentations from recognizable and innovative industry leaders. 

For any queries or additional information please email to vc-formal-india@synopsys.com.

Keynote Speakers

Sumit Goswami

Senior Director of Engineering, Qualcomm

Dr. Pallab Dasgupta

Head of Research and Innovation, Formal Verification, Synopsys

Agenda

Please check back to this page as we update our event agenda


Wed. September 25, 2024
09:30 - 10:00 AM IST
Registration Check-In
Wed. September 25, 2024
10:00 - 10:10 AM IST
Welcome Address
  • Synopsys
Wed. September 25, 2024
10:10 - 10:40 AM IST
Industry Keynote: Designing Next-Generation SoCs in a Correct-by-Construction Way
  • Sumit Goswami, Qualcomm
Wed. September 25, 2024
10:40 - 11:10 AM IST
Synopsys Keynote and Technology Innovation Session: Fashioning the Formal Technology Ramp ¨C The Beauty and the Beast
  • Dr. Pallab Dasgupta, Synopsys
Wed. September 25, 2024
11:10 - 11:40 AM IST
Gen AI-Powered Formal Verification Strategy: From Crawl to Flight!?
  • Anshul Jain, Intel
Wed. September 25, 2024
11:40 - 12:10 PM IST
Leveraging Formal Verification to Create, Reproduce, Verify Design Scenarios from Simulation Wave-dump
  • Ujjwal Talati, Synopsys
Wed. September 25, 2024
12:10 - 01:00 PM IST
Networking Lunch
Wed. September 25, 2024
01:00 - 01:40 PM IST
Tutorial: Shift Left Your Low Power Verification with VC Formal
  • Kamalesh Ghosh, Synopsys
Wed. September 25, 2024
01:40 - 02:10 PM IST
Datapath C/C++ vs RTL FV: Dream to Democratize
  • Disha Puri, Intel
Wed. September 25, 2024
02:10 - 02:40 PM IST
Effective Formal Signoff and Regression Strategies Tailored for Highly Parameterized Design
  • Brajmohan Sharma, Marvell
Wed. September 25, 2024
02:40 - 02:50 PM IST
Wed. September 25, 2024
02:50 - 03:20 PM IST
Who Watches the Watchman? FuSa Verification of DCLS Configuration through Formal and Static Checks
  • Avinash Pandey, Qualcomm
Wed. September 25, 2024
03:20 - 03:50 PM IST
Panel Discussion: Pushing Formal Verification Frontiers To Next Level
Wed. September 25, 2024
03:50 - 04:00 PM IST
Closing and Lucky Draw