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Synopsys¡¯ 30th Annual Test & SLM Special Interest Group (SIG)
Monday, November 4, 2024
6:00 p.m. - 9:30 p.m.
Hilton San Diego Bayfront, San Diego, CA? | Aqua Salon ABC (3rd floor)
Pre-registration has closed. Please complete the to be added to the waitlist. If a seat becomes available, you will be notified via email.
Walk-ins will be accepted onsite from 6:30 PM as space permits at the registration desk.
All members of the design and test community are invited to register to attend Synopsys¡¯ 30th Annual Test & SLM Special Interest Group (SIG) at the 2024 International Test Conference (ITC).
The event will host experts from leading companies who will share how Synopsys Test and SLM solutions including AI-driven test, distributed ATPG, high-speed test fabric, and automotive test are enabling them to achieve their quality and time-to-market goals.
Attendees will have the chance to engage with Synopsys experts to explore and gain insights into Test and SLM technologies. Appetizers and cocktails will be served, followed by a sit-down dinner and prize drawings!
Agenda
6:00 p.m. ¨C&²Ô²ú²õ±è;Cocktail Reception
6:45 p.m. ¨C&²Ô²ú²õ±è;Opening Remarks & Dinner
Yervant Zorian, Synopsys Fellow at Synopsys
6:55 p.m. ¨C&²Ô²ú²õ±è;Presentations
Silicon Health and Reliability - Multi-Die Joint Demo Vehicle Update ?
Sandeep Kumar Goel, Academician and Director at TSMC
A 2.5D DFT Implementation Experience for a Chiplet-based Multi-Die Package System ?
Kenichi Anzou, DFT Engineer, Methodology Development Office at Socionext Inc.
Harnessing the Power of Test Data Analytics in Heterogeneous Integration ?
Ira Leventhal, Vice President at Advantest
Diagnosis of Timing Margin in Silicon with Margin Monitors ?
Gurnrack Moon, Principal Engineer at Samsung System LSI
8:15 p.m. ¨C&²Ô²ú²õ±è;Moderated Q&A
Moderator: Yervant Zorian, Synopsys Fellow at Synopsys
8:30 p.m. ¨C Closing Remarks
Shankar Krishnamoorthy, Head of Technology & Product Development Group Staff at Synopsys
8:35 p.m. ¨C&²Ô²ú²õ±è;Networking Reception
Synopsys at International Test Conference (ITC)
Sunday, November 3 - Friday, November 8, 2024
Hilton San Diego Bayfront, San Diego, CA?
Exhibit Hours
Tuesday, November 5
10:30 a.m. - 5:30 p.m.
Wednesday, November 6
9:30 a.m. - 4:30 p.m.
Thursday, November 7
9:30 a.m. - 1:30 p.m.
Visit the Synopsys Booth
The Synopsys TestMAX? family provides cutting-edge test and diagnosis solutions for all silicon designs, seamlessly integrating with the Synopsys Digital Design Family. Synopsys TestMAX works in conjunctions with the Synopsys Silicon Lifecycle Management (SLM) solutions to enhance in-chip observability, silicon health, and analytics, simultaneously achieving both design and test objectives.
We will be highlighting silicon health and reliability in the age of AI systems in our booth (#115).
See demonstrations on:
- Path Margin Monitoring
- Clock and Delay Monitoring
- Test Optimization and Hyperconvergence
- Production Analytics
Let's Meet
Whether you want a quick chat to catch up or want to go deep on details, please reach out to us to schedule an on-site meeting.
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Tuesday Plenary Keynote
Shankar Krishnamoorthy
Head of Technology & Product Development Group Staff
Synopsys
Test and Telemetry in the Age of Pervasive AI
Tuesday, November 5, 2024
9:40 a.m. - 10:30 a.m.
Location: Sapphire-CDGH
The proliferation of silicon content in the age of pervasive AI means that test and telemetry is more important than ever in the development of software-defined systems. This silicon to systems approach is also driving multi-die innovation to solve the challenges around scaling and complexity as well as safety and reliability. In this keynote Shankar will also share his thoughts on the future of semiconductor test and discuss how AI will continue to shape and streamline Synopsys¡¯ innovative test and telemetry solutions over the next decade.
Sessions
Session Tutorial T5: AUTOMOTIVE FUNCTIONAL SAFETY USING PREDICTIVE MAINTENANCE
TTEP Tutorial by Yervant Zorian, Synopsys; Jyotika Athavale, Synopsys
Sunday, November 3, 2024; 1:00 p.m. ¨C 4:30 p.m. | Sapphire 410
Session Tutorial T7: 3DIC ADVANCED PACKAGING, TEST & SLM
TTEP Tutorial by Sandeep Goel, TSMC; Yervant Zorian, Synopsys
Monday, November 4, 2024; 8:30 a.m. ¨C 12:00 p.m. | Sapphire 400
Session Tutorial T10: UCIE 2.0 BASED MULTI-CHIPLETS DESIGN & TEST
TTEP Tutorial by Debendra Das Sharma, Intel; Yervant Zorian, Synopsys
Monday, November 4, 2024; 1:00 p.m. ¨C 4:30 p.m. | Sapphire 400
Session Tutorial T12: IN-FIELD SYSTEM TEST & DEBUG
TTEP Tutorial by Amit Pandey, Amazon; Karthik Natarjan, Synopsys; Sankaran Menon, Intel
Monday, November 4, 2024; 1:00 p.m. ¨C 4:30 p.m. | Sapphire 411
Session E1: Platinum Sponsor Presentation
Presentation by Synopsys
Tuesday, November 5, 2024; 4:30 p.m. ¨C 5:00 p.m. | Sapphire-CDGH
Session C1: Short Papers - Industrial Practices
Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests
Presenter: Moiz Khan, TSMC
Authors: Moiz Khan, Ankita Patidar, Frank Lee, and Sandeep Kumar Goel, TSMC; Vuong Nguyen, Bharath Shankaranarayanan, Doo Kim, and Manish Arora, Synopsys
Tuesday, November 5, 2024; 4:00 p.m. ¨C 4:20 p.m. | Aqua Salon AB
Session E2 ¨C UCIe Multi-Die Test
UCIe-based Open Chiplet Ecosystem: Architecture of Test, Debug and Silicon Lifecycle Management¡± Gerald Pasdast, Intel, Debendra Das Sharma, Intel, Yervant Zorian, Synopsys
Leveraging UCIe Interface for High-Speed Stack Testing of Chiplets in a 3D Stack¡±, Sandeep Goel, Ankita Patidar, Stanley John, Frank Lee, Min-Jer Wang, Daniel F.J. Yang (TSMC), Yervant Zorian, Manish Arora, Abhijeet Samudra, Shaan Awasthi, Stelios Balalis, Velmurugan Pathervellaichamy, Bharath Shankaranarayanan, Vidya Charan Chitti, Gurgen Harutyunian, Grigor Tshagharyan (Synopsys)
Wednesday, November 6, 2024; 10:30 a.m. ¨C 12:00 p.m.
Special Session: D5 ¨C SLM solutions for RAS
Addressing SDC challenges with Silicon Lifecycle Management, Yervant Zorian, Jyotika Athavale, Synopsys
Thursday, November 7, 2024; 10:30 a.m. ¨C 12:00 p.m.
Session B6: P1838a: Asked and Answered
Presentation by Adam Cron, Synopsys
Thursday, November 7, 2024; 2:00 p.m. ¨C 2:30 p.m. | Sapphire KL
Session C6: ChipAct Special Session
Panelists: Rob Aitken, CHIPS R&D Office; Krishnendu Chakrabarty, ASU; Jennifer Dworak, SMU; Yervant Zorian, Synopsys
Thursday, November 7, 2024; 1:30 p.m. ¨C 3:00 p.m. | Aqua Salon AB
Panel Session: Test Challenges in Chiplet based Design
Panelists: Srinivas Patil (Qualcomm), Yervant Zorian (Synopsys), Anshuman Chandra (Siemens Inc.) and Davide Apello (Technoprobe)
Friday, November 8, 2024; 11:00 a.m. ¨C 12:00 p.m.
New Silicon Health Challenges & opportunities with HBM4
Presenter: Yervant Zorian, Synopsys
Friday, November 8, 2024; 1:20 p.m. ¨C 1:40 p.m.
Workshops
4th IEEE Silicon Lifecycle Management Workshop
Presentation by General Chair: Yervant Zorian, Synopsys
Thursday, November 7, 2024; 4:00 p.m.
2nd Top Peaks in Test & Diagnosis, Workshop
Presentation by General Chair: Jyotika Athavale, Synopsys
Thursday, November 7, 2024; 4:00 p.m.
8th IEEE 3D & Chiplets TEST Workshop
Presentation by General Chair: Yervant Zorian, Synopsys
Thursday, November 7, 2024; 4:00 p.m.?
MultiDie Physical aware DFT
Presentation by Manish Arora, Synopsys
Friday, November 8, 2024; 3:00 p.m. - 3:30 p.m.
Posters
Wednesday, November 6, 2024; 12:00 p.m. ¨C 2:00 p.m. | Exhibit Hall-Sapphire ABEFIJMN |
Automation to Speed up the process of Timing Closure of the IJTAG Network
Authors: Kshitij Kulshreshtha, Amihay Rabenu, and Manish Arora, Synopsys
1687 Solution for Tiled Based Design with Feedthroughs
Authors: Vistrita Tyagi, Kshitij Kulshreshtha, Doo Kim, and Manish Arora, Synopsys
Enhanced Security Mechanism for 1687 Network
Authors: Kshitij Kulshreshtha, Vistrita Tyagi, Dipika Khandre, and Manish Arora, Synopsys
Scalable Multi-Chiplet Test Solution Using IEEE 1838
Authors: Vistrita Tyagi, Bharath Shankaranarayanan, Vuong Nguyen, Fengfeng Tang, and Manish Arora, Synopsys
Synergetic Pre- and Post-Silicon SLM Analytics for Reliable and Safe Automotive
Authors: Dan Alexandrescu and Lorin Kennedy, Synopsys
High-Performance ATPG with Loadable Nonscan Cells
Authors: Peter Wohl, Jonathon Colburn, John Waicukauski and Yasunari Kanzawa, Synopsys
Optimizing Mobile & Automotive GPUs with Streaming Fabric, SEQ/XLBIST, IEEE1687 and TSO.ai
Authors: Venkata Raja Ramchandar Koneru, Bala Tarun Nelapatla, Ricardo Godinez, Anand Gangwar, Jorge Corso, Rajkumar Pampana, Ashok Nandigam, Pramod Singh and Seongmoon Wang, Synopsys
For more information about Synopsys¡¯ comprehensive test solution, please visit: synopsys.com/test
