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Why Attend?
Synopsys is catalyzing the era of pervasive intelligence with comprehensive silicon to systems design solutions, from electronic design automation to silicon IP and system verification and validation. Join us at the Design Automation Conference (DAC) to hear expert insights through a multitude of sessions in the conference technical program as well as our booth. Don¡¯t miss the opportunity to gain critical knowledge to help power your innovation.
Synopsys at DAC 2024
Exhibits
Visit the Synopsys booth #2441 to network with our experts and see our demonstrations.
Exhibit Dates & Times:
- Monday, June 24, 2024: 10:00 AM ¨C 6:00 PM
- Tuesday, June 25, 2024: 10:00 AM ¨C 6:00 PM
- Wednesday, June 26, 2024: 10:00 AM ¨C 4:00 PM
Synopsys Demonstrations:
- AI-driven Productivity at Every Stage of Chip Design with Synopsys.ai
The award-winning Synopsys.ai EDA suite boosts productivity at every stage of chip design, providing comprehensive AI-driven design optimization, data analytics and generative AI capabilities. These AI-driven solutions optimize PPA, verification, test, and analog node migration; and analyze data to uncover actionable design insights, improve manufacturing yield, and increase chip quality. The suite¡¯s generative AI capabilities bring expert conversational guidance to every workflow to further accelerate design closure. In this demo, you¡¯ll experience the power of the full-stack Synopys.ai suite for AI-Driven Optimization (Synopsys DSO.ai, VSO.ai, TSO.ai, ASO.ai), Data Analytics (Synopsys Design.da, Fab.da, Silicon.da), and Generative AI including Synopsys.ai Copilot based on our collaboration with Microsoft.
- Robust Die-to-Die Connectivity with Synopsys UCIe IP
Used in multi-die designs, Synopsys UCIe IP provides industry-leading bandwidth, latency, and power for die-to-die connectivity in advanced and standard packaging technologies. Adopted in dozens of designs, the silicon-proven IP is scalable up to 24GT/s, with wide eyes and low BER, in multiple foundry process and packaging technologies. The Synopsys die-to-die IP solution also supports parallel interfaces with data rates up to 40GT/s. This demo features the Synopsys UCIe PHY IP showing better than 1E-18 performance with wide open eyes while operating at 24GT/s. The demo shows two implementations: 64 lanes for advanced packaging technology and 16 lanes for standard packaging technology.
- Advanced SoC HW/SW System Validation with Synopsys ZeBu? EP
Hardware-assisted verification helps verify software scenarios and enables longer running validation tests that cannot be run in a simulation environment. Synopsys ZeBu EP is the industry's only hardware-assisted verification platform that supports all use cases from RTL verification, SW bring-up, power and performance validation, protocol compliance and SW/HW system validation. This demo shows video codec and MIPI IP validation and SW/HW validation with waveform debug capability.
Synopsys Sessions & Presentations
Hear from Synopsys speakers at a variety of venues throughout the conference. View the full list of technical presentations and speaking appearances with our experts.
Synopsys Academic & Research Alliances (SARA)
Synopsys Academic & Research Alliances (SARA) was born through our commitment to growing relationships with universities beyond our University Software Program. Join us in celebrating students and professors at some of our sponsored events at DAC:
- Young Fellows Program
Synopsys is proud to co-sponsor the , which provides an opportunity to connect and interact with students and make a lasting impression on the next generation. As part of our commitment to empower future engineering talent, SARA will be present at the summer school on Sunday, June 23.
- Ph.D. Forum at DAC
at DAC is a poster session hosted by ACM SIGDA for Ph.D. students to present and discuss their dissertation research with the EDA community. Please save the date and time and join us as we recognize their work on Tuesday, June 25 at 7 PM.
- HACK@DAC
Synopsys is proud to sponsor ¡ªa competition focusing on penetration testing of hardware and firmware. Participants will compete to identify security vulnerabilities, implement the related exploit, propose a mitigation technique or a patch, and report them. Finalists will compete in a live capture-the-flag competition during DAC, and winners will be announced during DAC.
