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Synopsys IP Technical Bulletin - Q2 24

• ARC Zone: Generative AI for the Edge
• Understanding PCIe over Optics
• Enabling the USB4 v2 80Gbps Ecosystem
• Enabling the Integration of ADAS and IVI SoCs with Automotive-Grade IP
• Monitor, Test, and Repair Chips with Synopsys SLM IP
• Synopsys 3DIO Solution for Multi-die integration (2.5D/3D)

Synopsys IP Technical Bulletin - Q1 24

• ARC Zone: How the RISC-V ISA Offers Greater Design Freedom and Flexibility
• Navigating PCIe 6.0 Power and Latency Challenges in HPC SoCs
• How Direct-Drive Electro-Optical Interfaces are Changing the Game for 800G and Beyond
• Maximizing Performance & Reliability for Flash Applications with Synopsys xSPI Solution
• Bluetooth Use Cases for V2X Automotive Applications
• Synopsys and Intel Team Up on the First UCIe-Connected Chiplet-Based Test Chip

Synopsys IP Technical Bulletin - Q4 23

• ARC Zone: Integrating Functional Safety and Quality to Deliver High-Quality Automotive IP
• The Controller Designers Need for 1.6 Terabits per second Ethernet Interfaces
• PCI Express 6.0 for Automotive Applications
• Optimizing PPA for HPC & AI Applications with Synopsys Foundation IP
• Three Major Inflection Points for Sourcing Bluetooth Intellectual Property
• How LPDDR5X Delivers the Speed Your Designs Need

Synopsys IP Technical Bulletin - Q3 23

• ARC Zone: Virtualization Emerges as a Requirement for Embedded AI in Automotive SoCs
• Arriving at 224GbE: Double the Speed, Catapulting Complexity!
• CXL: How an Accelerator Link Caused a Memory Revolution
• Future Microcontrollers Need eMRAM
• CXL Applications and Opportunities
• How Technology and Workloads are Driving Multi-Die Systems

Synopsys IP Technical Bulletin - Q2 23

• ARC zone: AI Can See Clearly Now the Noise Has Gone - An Emerging Use-Case for Synopsys IP in Real-Time Video Enhancement
• Revving up Automotive Embedded Storage with UFS
• The Promise of ISO/SAE 21434 for Automotive Cybersecurity 
• Ensuring Multi-Die System Reliability with UCIe IP
• Living on the Computing Edge for 100G Ethernet IP

Synopsys IP Technical Bulletin - Q1 23

• ARC zone: Combining Neural Network Processors and DSPs to Achieve the Best AI Performance
  
• Benefits of a Silicon-Proven 800G Ethernet Implementation
• Ethernet Security Relies on Efficient Media Access Control Security (MACsec)
• TEE Device Interface Secure Protocol (TDISP) for PCIe and CXL
• PAM-3 Technology and Implementation for USB4 v2

Synopsys IP Technical Bulletin - Q4 22

• ARC Zone: The Expansion of Narrowband IoT: Addressing Low-Power Requirements with an Integrated Subsystem
• Secure High-Speed Interfaces with Ultra Low Latency Encryption & Authentication
• CXL 2.0 and 3.0 for Storage and Memory Applications
• Implementation Options for 112G Ethernet PHY IP

Synopsys IP Technical Bulletin - Q3 22

• ARC Zone: The Rise of Transformers: Greater Accuracy in Real-Time Vision Processing
• Achieving Systematic ASIL D ISO 26262 Compliance for Automotive SoCs
• Multi-Die SoCs Gaining Strength with Introduction of UCIe
• Protecting Data over PCIe & CXL in Cloud Computing
• Designing for Effective Use of PCIe 6.0 Bandwidth

Synopsys IP Technical Bulletin - Q2 22

• ARC Zone: New Neural Processing for Embedded Apps
• ARC Zone: Floating Point with ARC VPX Vector DSPs
  
• Can Chips Keep Up with AI Algorithms at the Edge?
  
• What Designers Need to Know About HBM3
  
• 112G Ethernet PHY Design Challenges and the Path Forward
  
• Memory Security Relies on Ultra High-Performance AES-XTS Encryption/Decryption
  

Synopsys IP Technical Bulletin - Q1 22

• ARC Zone: Meet Both Security and Safety Needs in New Automotive SoCs with ARC SEM130FS Processor
• PCIe PHY IP Enabling U.2/U.3 Form Factors for Hyperscale Data Centers
• An Insight into the World of 224Gbps Electrical Interface
• Why Large, High-Res Displays Need HDCP 2.3
• Selecting NVM IP for PMICs: 4 Key Considerations

DesignWare Technical Bulletin - Q4 21

• Insight into the OpenHBI Die-to-Die Standard
• Meeting Processor Performance and Safety Requirements for New ADAS & Autonomous Vehicle Systems
• ARC Zone: Implementing High Performance Sensor Fusion on an Embedded Budget, Using ARC VPX DSP IP
• Integrated MAC, PCS and PHY IP for 400G/800G Ethernet
• eMRAM for Low-Power SoCs in Advanced Process Nodes
• Under the Hood of ASIP Designer - Application-Specific Processor Design Made Possible by Tool Automation

DesignWare Technical Bulletin - Q3 20

• Advantages of Firmware-Based Training in High-Speed DDR IP
• Accurate Modeling and Integration Considerations for 112G SerDes PHY IP
• ARC Zone: Meeting Increasing Performance Requirements in Embedded Applications with Scalable Multicore Processors
• Production Test of System-in-Package with Die-to-Die PHY IP
• Upgrade Your SoC Design to USB4
• Selecting Memory Architectures for AI SoCs

DesignWare Technical Bulletin - Q2 20

• Estimating Power Early & Accurately for Smart Vision SoCs
• Parallel-Based PHY IP for Die-to-Die Connectivity
• ARC Zone: Addressing IoT Connectivity Challenges with a Low-power IoT Communications Solution
• A Few Key Features to Note About DDR5
• An Introduction to TCAMs
• Using Artificial Intelligence to Harness the Coming Data Explosion

DesignWare Technical Bulletin ¨C Q1 20

• How AI in Edge Computing Drives 5G and the IoT
• Choosing the Right IP for Die-to-Die Connectivity
• ARC Zone: Faster, More Accurate Data Computation with a New Generation of DSPs
• Key Features Designers Should Know About LPDDR5
• Maximizing Application Performance on ARC DSP Processors with the MATLAB/Simulink Plugin
• Techniques for Ensuring Security in Processor-based SoCs

DesignWare Technical Bulletin ¨C Q4 19

• Computer Vision: From the Lab to Your Life
• Designing Neural Network Architectures for Different Applications: From Facial Landmark Tracking to Lane Departure Warning System
• ARC Zone: Implementing Low-Power Machine Learning for Smart IoT Applications

DesignWare Technical Bulletin ¨C Q1 19

• High Accuracy Computer Vision with ISPs and Vision Processors
• Converging Cloud Computing Infrastructures with IP
• ARC Zone: Visualizing OpenVX to Optimize Vision Applications
• Accelerating 32 GT/s PCIe 5.0 Designs
• A Solid Foundation for AI-Powered SoCs
• Which SDRAM Standard to Use and When

DesignWare Technical Bulletin ¨C Q4 18

• Hyperscale Data Centers Driving Next-Generation 400G Ethernet Interconnects
• Meeting Complex Design Requirements for Integrated ADAS Domain Controller SoCs
• ARC Zone: High-Performance DSP and Control Processing for Complex 5G Requirements
• Scalability, Security and Reliability with One-Time Programmable Non-Volatile Memory
• Minimizing Security Vulnerabilities in Connected Cars Starts with Silicon
• High-Performance 91³Ô¹ÏÍø for Next-Generation SSD Designs

DesignWare Technical Bulletin ¨C Q3 18

• The DNA of an Artificial Intelligence SoC
• Why AI Needs Security
• ARC Zone: Flexible Processing for all IoT End Node Devices
• Building Efficient Deep Learning Accelerators from the Foundation Up
• Augmenting Your Reality with Deep Learning
• Hardware Mathematics for Artificial Intelligence

DesignWare Technical Bulletin ¨C Q2 18

• AI¡¯s Impact on Automotive IC Design
• Addressing Functional Safety in SoCs with Test 91³Ô¹ÏÍø 
• ARC Zone: Have Linux Your Way with the Yocto Project
• Ethernet Time-Sensitive Networking for Automotive ADAS Applications
• Data Converter IP for Automotive ADAS SoCs
• Integrated ADAS Domain Controller SoCs with ISO 26262 Certified IP

DesignWare Technical Bulletin ¨C Q1 18

• Implementing High-Performance Deep Learning without Breaking Your Power Budget
• HDMI 2.1 for a More Immersive Viewing Experience
• ARC Zone: Embedding Artificial Intelligence into Our Lives
• Synopsys and Arm Display IP Solution for 4K Smartphone and AR/VR Devices
• Challenges of Moving to 32GT/s PCI Express Designs

DesignWare Technical Bulletin ¨C Q4 17

• Understanding Hardware Roots of Trust
• Securing High-Value Targets with a Secure IP Subsystem
• ARC Zone: Easing Smart Automotive Design and Certification with High-Performance Processors for Safety-Critical Applications
• Using Threat Models and Risk Assessments to Define Device Security Requirements
• Bluetooth Mesh Drives Security
• eMMC and UFS Inline Encryption in Android-based Mobile Applications
  

DesignWare Technical Bulletin ¨C Q3 17

• An Introduction to CCIX
• Faster Time-to-Market for Mobile SoCs using USB Type-C
• ARC Zone: Addressing Embedded Challenges with Superscalar Mixed-signal Processors
• Visually Lossless Compression for UHD Displays
• High-Quality Automotive IC Design with IP Subsystems

DesignWare Technical Bulletin ¨C Q2 17

• Ensuring Content Protection over USB Type-C
• Bluetooth 5 Ready IP for IoT SoC Integration
• ARC Zone: Automotive Safety in High-Volume Applications
• The Evolution of Deep Learning for ADAS Applications
• 25G Ethernet IP for Higher Performance Data Center SoCs
• Overcoming Data Converters Design Challenges with IP in FinFET Processes

DesignWare Technical Bulletin ¨C Q1 17

• New USB Audio Class for USB Type-C Digital Headsets
  
• Facial Expression Analysis with Deep Learning & Computer Vision
  
• ARC Zone: Advanced Processors Enable Seamless Human-Machine Interfaces for Virtual Reality
• Understanding the Ethernet Nomenclature - Data Rates, Interconnect Mediums and Physical Layer
  
• Using Foundation IP for Low Power in IoT SoCs

DesignWare Technical Bulletin ¨C Q4 16

• PCI Express 4.0 Lane Margining and its Advantages
• Understanding Automotive DDR DRAM
• Getting Optimal PPA for 16FFC SoCs
• Implementing MIPI Camera and Display Interfaces in Applications Beyond Mobile
• Challenges of USB 3.1 Host Certification
• Advantages of Integrating Bluetooth Low Energy IP into a Single SoC
• ARC Zone: Protecting Against Side-Channel Attacks with an Ultra-Low Power Processor

DesignWare Technical Bulletin ¨C Q3 16

• PCI Express in Automotive Applications ¨C Design for Reliability
• Enabling Cars to See with Efficient Vision Processors
• Best Practices for ISO 26262 ASIL Ready Automotive ADAS SoCs
• Accelerate Your Design Schedule with Automotive-Qualified Reprogrammable Non-Volatile Memory IP
• Reach Your ASIL Targets with Certified Ethernet IP
• ARC Zone: Choosing an Embedded Processor for Safety-Critical Automotive Applications

DesignWare Technical Bulletin ¨C Q2 16

• Challenges of USB 3.1 IP Certification
• Implementing Large Numbers of Virtual Functions with PCI Express SR-IOV
• Accelerating Cryptographic Operations in the TLS Protocol
• Wired 2.5G/5G Ethernet Speeds for Faster Wireless Connectivity
• ARC Zone: Accelerating IoT Applications with a Data Fusion IP Subsystem

DesignWare Technical Bulletin ¨C Q1 16

• Secure IoT System Boot with a Hardware Root of Trust
• Enabling Wireless Connectivity in Energy-Efficient IoT Designs with Bluetooth Smart IP
• Flexible Internal & External Connectivity for IoT Applications
• Memory Options for the IoT
• Using Foundation IP for Low Power in IoT SoCs
• ARC Zone: Balancing Security Requirements with Power and Area Constraints for IoT Edge Devices

DesignWare Technical Bulletin ¨C Q4 15

• Power Gating: Reducing PCI Express Power Consumption to Mobile Levels
• Developing Software for Proprietary Cameras for Integration with CSI-2 Host IP Prototyping Kits
• Understanding Advanced Interconnect IP Peripherals for IoT and Automotive SoCs
• Configuring DDR Subsystems for Your Design
• ARC Zone: Processor Configurations for Low-Power IoT Applications

DesignWare Technical Bulletin ¨C Q3 15

• Implementing USB Type-C in High-Speed USB Products
• 6 Logic Library Capabilities to Improve PPA on TSMC 28HPC+
• eMMC: Low-Power Mobile Storage for Smartwatches
• Control Design Precision: DesignWare Foundation Cores
• Accelerate Time-to-Market with Interface IP Subsystems

DesignWare Technical Bulletin ¨C Q2 15

• Embedding Vision in Next-Generation SoCs
• DesignWare Hybrid IP Prototyping Kits for Prototyping, Software Development & Integration in 64-Bit ARM Processor-Based Designs
• Multicore Design Using ASIPs: Blending Performance and Efficiency with Programmability
• Understanding Your Power Profile from RTL to Gate-level Implementation
• 25G Ethernet in the Connected World

DesignWare Technical Bulletin ¨C Q1 15

• RAS Data Protection Consideration for PCI Express? Designs
• IP Subsystems: The Next Frontier for IP Integration 
  
• Faster Iteration Flows to Accelerate Hardware/Software Development
  
• Converting Existing USB Designs to Support USB Type-C Connections
• Advantages of Embedded MTP Non-Volatile Memory for IoT SoC Designs
• Is the FinFET Process the Right Choice for Your Next SoC?
• ARC Zone: Configurable & Extensible 32-bit RISC Processors for Next Generation SSDs
  

DesignWare Technical Bulletin ¨C Q4 14

• USB 3.1: Physical, Link, and Protocol Layer Changes
• HDMI and MHL IP for Mobile and Digital Home Connectivity
• Assess Analog Front-End Performance in Communication SoCs
• Verifying ARM AMBA ? 5 CHI Interconnect-Based SoCs Using Next-Generation VIP
• LPDDR4 for a Better Power/Performance Balance
• ARC Insider: Designing Processors for High-Performance Embedded Linux Applications

DesignWare Technical Bulletin ¨C Q3 14

• ARC Insider: Low-Power Processor 91³Ô¹ÏÍø for Always-On Devices
• IP Accelerated: IP Integration with Less Effort, Lower Risk, and Faster Time-to-Market
• Design Considerations for Non-Volatile Memory IP in Automotive Applications
• Designing for Success: USB IP for FinFET Processes
• PCI Express Controller Design Challenges at 16 GT/s
• What's New in Verification IP?

DesignWare Technical Bulletin ¨C Q2-14

• ARC Insider: Top 5 Features to Consider When Choosing a Software Development Platform
• Optimized Memory Hardening for CPU, GPU and DSP Cores
• Understanding the MIPI M-PHY
• Developing High-Performance 28-nm Data Converters with the SAR-Based Architecture
• USB 3.1: What's in a Name?
• Tips & Tricks: Techniques for Improving QoR Using analyze_datapath_extraction

DesignWare Technical Bulletin ¨C Q1-14

• Optimizing High-End Embedded Designs with the ARC HS Processor Family
• Demystifying 40 Gigabit Ethernet Interfaces in Data Centers
• What's New with DesignWare Building Blocks and minPower Components in I-2013.12?
• Delivering on the Promise of Guaranteed Isochronous Traffic in USB 3.1
• ARC Insider: Automotive Safety: Achieving ISO 26262 Compliance with Processor IP Part 2

DesignWare Technical Bulletin ¨C Q4-13

• Adapting Non-Volatile Memory to Evolving Markets
• Quality of Service in DesignWare AMBA AXI Interconnect
• Achieving 10 Gbps Data Rates in USB 3.1 Using Multiple INs and Hub Playload Buffering
• ARC Insider: Automotive Safety: Achieving ISO 26262 Compliance with Processor IP
• Tips and Tricks: Guidelines for Successful IP Integration and Tapeout

DesignWare Technical Bulletin ¨C Q3-13

• Simplifying Sensor Integration with the DesignWare Sensor IP Subsystem
• Optimizing CPUs, GPUs and DSPs for High Performance and Low Power at 28nm
• Bandwidth Considerations for PCI Express 3.0 Designs
• Modern FPGA-Based Prototyping Systems Accelerate the Transition from Stand-Alone IP Block Validation to Integrated Systems
• MHL vs. Miracast
• Tips and Tricks: Using Buildroot to Build an Embedded Linux System for DesignWare ARC? Processors

DesignWare Technical Bulletin ¨C Q2-13

• DDR4 Bank Groups in Embedded Applications
• Using Port Multipliers with a SATA Host for Higher Performing Storage
• Dolby MS11 Decoder for DesignWare ARC Audio Processors
• Tips and Tricks: Prototyping Your USB 3.0 System in a HAPS Environment

DesignWare Technical Bulletin ¨C Q1¨C13

• FinFET Design, Manufacturability, and Reliability
• Embedded Memory Test & Repair at 20-nm Nodes and Below
• Efficient Audio Processing with DesignWare ARC? Audio Processors
• Ethernet QoS v4.0 Controller for 802.1 Compliant Networks
• Virtualizer Development Kits: Fast Track to DesignWare Software Prototyping
• Transitioning from USB 2.0 HSIC to USB 3.0 SSIC

DesignWare Technical Bulletin - Q4-12

• Using L1 Sub-States to Reduce Power Consumption in PCI Express?-Based Devices
• HDMI Fast Switching
• Performance and Coding Advantages with the ARC? XY Memory DSP Option
• Interfacing an SoC to the Real World with Data Converter IP
• MHL: The New Mobile-to-TV Protocol

DesignWare Technical Bulletin ¨C Q3-12

• Selecting Standard Cell and Memory IP to Meet Chip Goals
• Managing Design Complexity with a Complete Audio IP Subsystem
• Building an IP-XACT Design and Verification Environment with DesignWare IP and core Tools
• A Simple Way to Use DesignWare Libraries in FPGA-Based Design Prototypes
• Synopsys Verification IP, What's New?