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Introduction

The key to designing semiconductor products for the high-volume automotive market is to meet the demanding requirements of a harsh environment without over designing the IC. This article will focus on the balancing act required to design non-volatile memory (NVM) for automotive Grade 0 applications that exceed quality and reliability criteria established for the extreme environment under the hood of a car, while respecting the cost and size parameters of even the smallest ICs. It will also cover the identification of critical test modes and developing a test flow that cuts test times by a factor of three over past NVM IP designs. 

Need for Re-programmability in Automotive Applications

In the evolving automotive market, the demand for more and smarter ICs is skyrocketing. Smarter ICs have an increased need for non-volatile memory, specifically reprogrammable NVM. Reprogrammable NVM IP¡¯s use goes beyond code storage. Sensing, power management, and wireless connectivity devices use NVM for calibration, configuration, data logging, user settings, and storing security information. In addition, reprogrammable NVM helps to ensure quality. Before an IC goes into a car, multiple rounds of testing and tightening of specifications require information to be changed in the test cycle. As not all of these functions require or can afford embedded Flash, other technologies must be considered.

As an example automotive application, we can look at sensors. There are many sensors used in today¡¯s cars, such as Hall sensors for anti-lock brake systems and pressure sensors in the intake manifold, and many of these sensors drive mission-critical functions. As the sensors must be calibrated to stay within a tight tolerance regardless of manufacturing variability, NVM is used to store this information with high reliability. Figure 1 shows the steps along the sensors¡¯ life cycle in which calibration data must be changed and stored, including the silicon manufacturing process, the electronics assembly, and the manufacturing of the car itself. Even after the car rolls off the manufacturing line, calibration data may need to be rewritten to recalibrate a sensor that has demonstrated a drift in specification parameters. This drift is common in automotive spaces due to the long life of a car or truck.

Designing NVM IP with Automotive Markets in Mind

High-reliability NVM starts at the IP design phase where a clear understanding of the process technology and the product requirements enable IP vendors to design a product that meets the reliability targets of the IC within the most efficient power consumption and area budgets.

Consider data retention, which is the ability of an NVM array to retain information when the IC is not powered on. In the case of floating gate based memory technology, a bit is stored using the presence (absence) of charge, leading to a more positive (negative) threshold voltage. To retain this information, the gate must be able to hold charge. Figure 2 shows a floating gate with surrounding dielectrics. The thickness and properties of these dielectrics define the inherent capability of a process to retain charge (also called intrinsic retention). Electrons will take the path of least resistance to escape, so any layer surrounding the gate could be the weakest link. NVM developers with experience with the process technology to be used can address potential vulnerabilities early, either through design or process tweaks.

While excellent intrinsic retention is necessary, the reliability of an NVM array is only as good as the performance of its weakest bit. To achieve the zero-defect reliability goal of the automotive market, the design needs to focus on handling the weak bits that are most susceptible to fail. IP vendors can implement one or several architectural methods to improve overall IP reliability, such as:

• Integrate error correction (ECC) functionality. The addition of parity bits to each word can be used to detect and correct single bit errors.
• Implement a differential bitcell architecture (Figure 3). This architecture employs two floating gates per bit to provide 100% redundancy at the bitcell level. This technique is extremely reliable as both floating gates would independently have to lose/gain enough charge to flip the bit-cell state. Using a differential bitcell rather than ECC is area effective at small bit counts.
• Combine both a differential bitcell and error correction. A combination approach is necessary for processes where the incidence of extrinsic bits is high.

When designers implement a bitcell architecture, their IP design needs to consider the product requirements in term of write cycles (endurance) and operating temperature (i.e., Grade-0,1,2,3,) as endurance has a profound effect on the speed and complexity of the erase (program) algorithm. High voltages are applied to the bitcell during the erase (program) operation, which can damage the bitcell. The designer needs to mitigate the impact of those high voltages on the target bitcell to avoid creating additional weak bits, as well as on the entire NVM array to avoid disturbing previously written data. In general, products requiring fewer write cycles (e.g., 1k cycles) will tolerate:

• Faster write time
• Higher operating temperature (150¡ãC and above)
• Simpler erase (program) algorithm

NVM IP design architecture choices combined with the intrinsic properties of the process impact the reliability of the end product, and thus must be considered upfront and in combination when designing for automotive markets. Non-volatile memory IP designers must make architectural choices that will meet the needs of the end application, including size, cost, quality, and reliability. This balance can best be achieved leveraging experience and history with both the process and NVM architecture.

Creating an Automotive Production Test Flow for Optimal Test Times

As no process is perfect and defects are a fact of life, a comprehensive and efficient production test flow is needed to weed out failing parts before they are delivered to the end customer. Reprogrammable NVM offers a key advantage for the automotive market in that each and every bit can be tested, thereby increasing the confidence that the IC will perform as expected in the field.

A comprehensive production test strategy may include multiple test sequences, such as:

1. Wafer level functionality test ¨C screen out defective parts
2. Retention bake ¨C screen out weak bits that do not hold charge
3. Package level functional test ¨C validate IC functionality across temperature
4. Burn-in ¨C weed out infant mortality

The above approach is comprehensive but costly. To reduce the test cost, the IP provider should implement special test modes to speed up test time and recommend a focused test strategy. For example, rather than programming each row sequentially, bulk operation should be designed in to allow programming of the entire array in a single operation. Similarly, rather than programming each and every row to a unique pattern to validate address uniqueness, a clear understanding of the address decoding allows for a more targeted approach by selecting few addresses while achieving equivalent test coverage. In addition to these techniques, test conditions and test limits should be selected so as to emulate temperature effects with a goal of eliminating the need for testing across temperature.

Meeting Cost and Size Constraints

As in any high volume business, automotive markets demand cost-effective solutions. Also, as many of these components fit into tight spaces, like in the wheel or mirror, size constraints limit the area available for memory and impact tradeoffs that can be made. However, automotive applications accept no relaxation in the quality or reliability of the components to reduce size and cost. To accomplish this feat, IP designers consider both parameters in every step of the development process, from product definition and product design to test flow:

• Product definition: Specifications should be as market-specific as possible to avoid over design
• Product design: Architectural choices based on experience and simulations balanced with process understanding create enough margin to achieve high yield with strict test limits¡­but also not excessive margin that inflates size and cost. Sometimes an iterative approach is necessary to optimize the design.
• Test flow: Testing must comprehend critical failure modes and the quickest way to find them.

Confirming Success through Testing

High-reliability NVM begins with design and architecture considerations, but is ultimately validated through silicon testing. Prior to going into production, a thorough testing methodology is required to satisfy the automotive industry, including:

1. Characterization: Validation of the product performance and its margin relative to the specification across process splits, mimicking expected manufacturing variations. For example, the most stringent automotive products (Grade 0), which are rated for operation at 150¡ãC, are tested at temperatures of 165¡ãC or even 175¡ãC to demonstrate margin.
2. Qualification: Stress tests focused on the reliability specification. The qualification test flow should be designed with a keen understanding of the potential failure modes while meeting or exceeding industry standard requirements.
3. Reliability projection: Extended reliability stresses, modeling, and failure rate projections based on bit level statistic data.

When the IC developer is an IP supplier, the supplier¡¯s silicon data can be used to augment or replace the IC designer¡¯s reliability test data, thereby reducing effort and overall cost of the project. For more details on Synopsys¡¯ testing methodology for NVM IP, please see the whitepaper, ¡°Developing High-Reliability Reprogrammable NVM IP for Automotive Applications¡±.

DesignWare Multiple-Time Programmable NVM IP

Synopsys has over 10 years of experience developing reprogrammable NVM IP, including the development and production release of IP that is specifically designed for automotive grade 0 applications supporting temperatures up to 150¡ãC. Leveraging this experience, Synopsys has reduced the area required by an automotive qualified IP by 75% and reduced the test time by 3x without impacting the overall quality and reliability of the end product.