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Introduction
The USB4 version 2.0 standard allows a port or cable to transfer data at 80Gbps, which is double the existing USB4 data rate of USB 40Gbps. The goal for USB4 v2 is to re-use the existing USB Type-C? cables and connectors. Doubling the speed from 20Gbps/lane to 40Gbps/lane using existing Pulse Amplitude Modulation 2-Level (PAM-2) is not possible without significant upgrades to the USB-C? connector and cables. As data rates go up, the cables and connectors introduce higher attenuation, increased noise, and more crosstalk. To solve this similar type of problem, PCIe 6.0 and 112G Ethernet standards use PAM-4 with 4 different voltage levels and a much smaller eye opening. PAM-3 for USB4 v2 provides larger eye openings and easier implementation compared to PAM-4. With PAM-3, the symbol rate increases from 20Gbps symbols to 25.6Gtps, which multiple independent vendors confirm to be feasible using existing USB-C cables and connectors. This enables USB4 v2 to be introduced without changes to the existing USB-C infrastructure, just like USB4 originally re-used the existing USB 3.2-based USB-C infrastructure.
This article describes the new PAM-3 modulation for USB4 v2 and some of its implementation challenges.
PAM-3 Encoding and Decoding
In previous USB standards, PAM-2, often called NRZ modulation encodes payloads consisting of words to serialized binary data using two signal levels. With PAM-3, words must be encoded onto 3 different signal levels. For USB4 v2, PAM-3 is achieved with a 11b/7t encoder for transmit and corresponding 7t/11b decoder for receive. For transmit, 11 binary digits corresponding to 2048 different values are encoded to 7 ternary digits which can represent 2187 different values. Since only 2048 values are needed to convey data, some of the unused values are used for control. 11b/7t encoding has less overhead than 8b/10b encoding as used for USB 3.0, or 128b/132b encoding as used for USB 3.1/3.2 and USB4.
To reduce the occurrence of error propagation causing burst errors with use of multi-tap Decision Feedback Equalization (DFE), precoding is used. Precoding moves bits from their sequential position in the bit-stream and spreads them across a larger part of the bitstream. The benefit of precoding is that a multi-bit error burst is converted to a single bit error at the start, and a single bit error after the error burst. The uncorrected Trit Error Rate for PAM-3 at 25.6Gtps using existing USB-C channel models was found to be ~1E-8 which is significantly worse than USB4 Bit Error Rate. USB4 v2 therefore mandates the use of Forward Error Correction (FEC) for PAM-3. Reed-Solomon (480,504) FEC detects and corrects up to 12 errors per block. Combined with precoding, the resulting BER of 1E-19 is significantly better than 1E-12 for USB4 Gen3 20Gbps.
PAM-3 Transmit and TX Equalization
The USB4 v2 signal goes through a channel that is not ideal. High frequencies are attenuated more than low frequencies in the chip, chip package, circuit board, connectors, and cables causing high frequencies to be more susceptible to noise and more difficult to receive. Some might remember listening to vinyl records that used Recording Industry Association of America (RIAA) equalization. When recording, low frequency signals were attenuated, and high frequency signals were boosted to better match the physical medium. USB3, USB4 and USB4 v2 transmit use a very similar approach!
USB 3.2 Gen2 10Gbps uses a single fixed frequency response adjustment when transmitting. A single bit that changes, which corresponds to high frequency, is boosted while sequential bits that do not change, which corresponds to low frequency are attenuated, as illustrated in Figure 1.
Figure 1: USB 3.2 Gen2 10Gbps Transmit Equalizer
Source: USB 3.2 specification revision 1.1 June 2022, Figure 6-23
https://www.usb.org/document-library/usb-32-revision-11-june-2022
USB4 Gen2 10Gbps and USB4 Gen3 20Gbps use one of 16 presets. The frequency response for the 16 presets for USB4 Gen3 20Gbps are shown in Figure 2. Preset0 is linear frequency response while preset 15 is approximately half the amplitude for low insertion loss channels. This prevents the receiver from being overdriven.
Figure 2: USB4 Gen3 20Gbps TX presets
Source: USB4 version 2.0 specification October 2022 figure 3-14
https://usb.org/document-library/usb4r-specification-v20
The reason why USB4 Gen2 10Gbps uses 16 presets versus USB 3.2 Gen2 10Gbps single preset is to enable better adaptation to the actual channel for each connection. This is required since USB4 Gen2 10Gbps must work over the same cable as USB 3.2 Gen1 5Gbps. Likewise, USB4 Gen3 20Gbps must work over the same cable as USB 3.2 Gen2 10Gbps. The USB4 v2 specification defines 42 presets for the USB4 Gen4 40Gbps data rate. Although link training becomes more complex, the link quality improves and ensures a robust and stable connection.
Actual implementation using a hybrid (voltage/current) transmitter (TX) driver with programmable boost and attenuation becomes complex when multiple, accurate presets must be supported. For USB4 v2 TX, an alternate solution is an Infinite Impulse Response (FIR) filter in the digital domain, and a DAC-based driver instead of a complex hybrid analog driver.
PAM-3 Receive and RX Equalization
Typical USB 3.2 Gen1 5Gbps implementations have a simple receiver (RX) boost that can be enabled if needed for the actual channel. USB 3.2 Gen2 10Gbps uses 5 different RX equalization settings, and DFE. Bits passing through a non-ideal channel are influenced by previous bits due to symbol interference. DFE lowers or increases the slicing amplitude for the current bit, in other words DFE takes into account previous bits when decoding the current bit. The reference receiver for USB 3.2 Gen2 10Gbps is 1-tap DFE, but typical implementations use 2 or 3-tap DFE for better performance.
USB4 Gen2 10Gbps and Gen3 20Gbps have even larger number of RX boost settings. The reference receiver defines 10 different settings and 1-tap DFE but again, actual implementations might use 3-tap DFE for better performance. Figure 3 shows the frequency response of the USB4 Gen3 20Gbps reference Continuous Time Linear Equalizer (CTLE).
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Figure 3: USB4 Gen3 20Gbps reference CTLE frequency response
Source: USB4 version 2.0 specification October 2022 figure 3-7
https://usb.org/document-library/usb4r-specification-v20
To decode PAM-3 signals, an additional slicer is needed to decode two eyes. See figure 4 for a typical PAM-3 signal and the defined signal levels. For PAM-3, the ideal slicing levels are between V0 and V1, and between V1 and V2. For USB4 v2 Gen4 40Gbps, the reference receiver is defined in a way that allows actual implementations to fit each vendor¡¯s proprietary technology.
Figure 4: PAM-3 constellation levels
Source: USB4 version 2.0 specification October 2022 Figure 3-29
https://usb.org/document-library/usb4r-specification-v20
USB4 v2 PHY Multi-Mode Operation
As with all previous USB specifications, backwards compatibility is vital. A new USB host must still support older standards, and new USB devices must still work with older hosts. This ensures end-user satisfaction and reinforces the message ¡°It¡¯s USB ¨C it just works¡±. This means that a USB4 v2 PHY must still support all the legacy USB3 and USB4 speeds, and DisplayPort 1.4 Alternate Mode. In addition, USB4 v2 supports tunneled DisplayPort 2.1 and DisplayPort 2.1 Alternate Mode. Support for the new Asymmetrical mode with 120Gbps TX/40Gbps RX using 3 of the 4 lanes for TX is expected even if not mandatory.
Table 1 shows the USB-C lane usage and USB4 v2 PHY configurations for legacy USB, DisplayPort, Thunderbolt, USB4 and USB4 v2. An even more complex USB4 v2 PHY is required for USB4 v2 re-timer which adds DisplayPort RX and reverse asymmetric mode (40Gbps TX and 120Gbps RX) support.
Table 1: USB-C Lane Usage for USB4 v2
Summary
To support new use cases, including blazingly fast storage and multiple high-resolution, high refresh rate displays, USB needs to support faster data rates. Today, USB4 v2 doubles the speed of USB4 to 80Gbps. The deployment of USB4 80G is expected to take off soon, however, designers need to understand some of the key implementation challenges of USB4 v2 due to the new PAM-3 signaling. Binary to ternary encoding, decoding, more advanced TX and RX equalization, and the use FEC are all changes USB designers must understand.
Synopsys is a major contributor to the development of the USB standards across all the generations. Synopsys offers the world¡¯s most preferred and most widely used USB Controller and PHY IP from USB 1.1 to USB4 v2. Contact Synopsys for further information on how we can help kickstart your next design.
Resources
Synopsys USB 80Gbps Blog:
USB4 v2 Specification:
Synopsys USB IP: /designware-ip/interface-ip/usb.html
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