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By: Morten Christiansen, Technical Marketing Manager for USB & DisplayPort, Synopsys

Portable devices have become lighter, thinner and more powerful with each generation. The latest phones, advanced tablets, hybrid laptops and ¡°anybooks¡± support new consumer requirements for legacy laptop replacement and all-day productivity without charging. However, most internal space for these devices is allocated to the battery, leaving little room for the other electronics. Therefore, system-on-chip (SoC) designers must integrate more functionality, minimize SoC pin counts and trim the number of connectors. USB Type-C^TM is the preferred connector for these thin, powerful mobile devices, supporting data, audio, video and power through a single connection. This article describes how SoC designers can accelerate design development by taking advantage of a pre-configured and pre-integrated USB-C 3.1/DisplayPort solution, including USB 3.1, DisplayPort 1.4 TX, DisplayPort AUX, HDCP 1.4 controllers, HDCP 2.2 Embedded Security Modules and USB 2.0, USB 3.1, DisplayPort TX and DisplayPort AUX PHYs, in addition to verification IP and test-cases. Adopting the DesignWare? USB-C 3.1/DisplayPort solution (Figure 1) reduces IP configuration, integration and verification efforts and enables designers to meet time-to-market needs while minimizing external, on-board components and product bill-of-materials (BoM) costs.

Figure 1: DesignWare USB-C 3.1/DisplayPort Solution

Market Overview and New Use Models

In the not too distant past, phones were used for messaging, phone calls and the occasional game of Snake or Tetris. PCs were used for web surfing, gaming, email, office applications, and storing and light editing of pictures, and DVD playback was a sensation. Today the boundaries between phone and PC are blurred; advanced phones are used for surfing, email, and office applications, takes great pictures and enables shooting, editing and playback of High-Definition (HD) video. The first phones with 4K Ultra High-Definition (UHD) displays have just been announced. Advanced tablets and hybrid laptops are replacing legacy laptops. Compute sticks with processor, memory and storage enable a portable and complete computing environment experience in any location that can provide a display and keyboard. The first 50 Mpixel still image camera is old news, and new video cameras are designed to shoot 8K video.

SoC system architects for these types of products are tasked with difficult use-case scenarios, feature implementations, and system design and partitioning choices. SoC designers must handle complex IP configuration, integration and verification tasks while meeting time-to-market requirements. Due to the high cost of SoC development, SoC re-use for different types of products is important. Advanced phone chipsets are designed for phones, portable augmented reality (AR) and virtual reality (VR) products, cameras, tablets, and even laptops using the ARM? version of Windows 10. End-users now expect the same functionality and use-case support regardless of product type or form factor. 

DisplayPort without an Analog Switch/Multiplexer

The first products supporting DisplayPort Alternate Mode on USB Type-C connector did so by multiplexing legacy DisplayPort and USB ports with external multiplexers, which added to PCB area, BoM cost and power consumption. To reduce SoC silicon area, SoC pin-count, PCB area, power and product BoM cost, new SoCs must include a single USB/DisplayPort port that connects directly to the Type-C connector.

The Synopsys DesignWare USB-C 3.1/DisplayPort solution includes a USB/DisplayPort comboPHY with digital multiplexer or crossbar switch that supports USB 3.1 Gen2 at 10 Gbps and DisplayPort HBR3 (HighBitRate3) at 8.1 Gbps. The digital crossbar switch (Figure 2) ensures optimal signal integrity for these high bit rates.    

High Resolution Displays and Display Stream Compression

Today, Full HD (FHD) TVs (1920x1080) are found in almost every living room, and FHD or Quad HD (QHD) (2560¡Á1440) monitors are common in both office and home. When shopping for a new TV, customers find that 4K UHD (3840x2160) TV sets are plentiful and affordable. 4K monitors are becoming the new office standard. New SoC designs should even consider supporting next generation 8K UHD (7680x4320) displays.

The DesignWare USB-C 3.1/DisplayPort solution supports DisplayPort 1.4 and is backwards compatible with DisplayPort 1.3. The DisplayPort 1.3 standard with 4 lanes of HBR3 supports 4K/RGB/60Hz or 90Hz and 8K/YUV/30Hz. To support 4K/120Hz and 8K with higher refresh rates and/or RGB format, Display Stream Compression (DSC) is used. DSC is visually lossless compression and is the main enhancement to DisplayPort 1.4 specification. Figure 1 shows that DSC is an integrated part of the DesignWare USB-C 3.1/DisplayPort solution. Be aware that DSC implementations require a fairly high gate count, and because of this, few of today¡¯s displays support DSC. However, DSC is expected to be required for high resolution/high refresh rate VR/AR applications.

One challenge for supporting high resolution displays is the pixel rate. 4K/120Hz and 8K/30Hz is a nominal 1188MHz while 8K/60Hz is 2376MHz pixel rate. The DesignWare DisplayPort 1.4 TX controller includes an option for a multi-pixel interface that reduces pixel rate on the DisplayPort TX video interface to, for instance, 594MHz.

Content Protection with HDCP 1.4 and HDCP 2.2

When displaying premium content, the link between the source and the display must be protected. HDCP 1.4 is required to support HD and FHD resolutions and is included in the DesignWare DisplayPort TX controller. HDCP 2.2 is required for 4K UHD and 8K. For security reasons, HDCP 2.2 Embedded Security Module is external to the DisplayPort TX controller in the DesignWare USB-C 3.1/DisplayPort solution (Figure 1). However, HDCP 2.2 ESM is a fully integrated part of the solution for ease of SoC integration and verification.

Supporting Multiple Displays

Multiple monitors are common in office environments, and to support this consumer need, the DesignWare USB-C 3.1/DisplayPort solution supports DisplayPort Multi Stream Transport (MST). MST enables one source to drive multiple monitors from one connector. Monitors with MST support are daisy-chained. Monitors without MST support connect as the last monitor in the MST daisy-chain or connect to a DisplayPort hub. The DesignWare USB-C 3.1/DisplayPort solution supports from one to four streams with equal resolution. Total available bandwidth is shared between the monitors; for instance, four FHD monitors are supported with four lanes of HBR2 without DSC.

Simultaneous USB and DisplayPort

Figure 2 shows the USB, DisplayPort and simultaneous USB and DisplayPort modes supported on the Type-C connector. Not all current DisplayPort Alt Mode implementations support simultaneous USB and DisplayPort. Also, many current Type-C implementations are limited to USB 3.0 5G and DisplayPort 1.2 HBR2 5.4 Gbps. Even if USB 2.0 is still available in DisplayPort (only) mode, this is limiting for some Type-C use-cases. The DesignWare USB-C 3.1/DisplayPort Solution fully supports simultaneous 10 Gbps USB 3.1 and 2 lanes of DisplayPort 1.4 HBR3 8.1Gbps/lane, enabling 4K UHD monitor support with simultaneous 10 Gbps file transfers and high bandwidth networking.

Figure 2: USB/DisplayPort lane multiplexing and crossbar switch for USB Type-C connector

Virtual Reality and Augmented Reality

VR and AR are becoming an important application for product developers. For an immersive VR/AR experience, high resolution and high refresh rates are required. Support for HBR3 enables this, even without DSC. For future higher resolution AR/VR applications, DSC will be required. The DesignWare USB-C 3.1/DisplayPort solution supports legacy 3D formats, side-by-side full resolution (left and right, or MST) as required for different AR/VR applications and implementations.     

Supporting External USB Type-C ICs

The USB Type-C connector has separate pins for Configuration Channel, Power Delivery messaging and Vconn power to adapter cable, also known as Type-C Port Controller (TCPC) hardware. TCPC hardware is not suited for SoC implementation in advanced process nodes due to high voltage and power consumption. Even if parts of the TCPC hardware can be integrated in SoC, multiple external discrete components and additional SoC pins make such implementations un-competitive compared to a standalone, cost optimized Type-C IC. TCPC hardware can also be integrated in a Power Management IC (PMIC) for lowest possible system cost.

Multiple vendors provide standalone, highly integrated and feature-rich Type-C chips. Some chips allow a processor in the SoC to execute the required Type-C software stack also known as Type-C Port Manager (TCPM). Other Type-C ICs are complete with a microcontroller, embedded RAM/Flash memories and certified TCPM software and TCPC hardware. The DesignWare USB-C 3.1/DisplayPort solution provides software and hardware interfaces to standard USB Type-C ICs. 

DesignWare USB-C 3.1/DisplayPort Solution Environment

The complete DesignWare USB-C 3.1/DisplayPort solution is shown in Figure 3. All controllers, PHYs, interconnects, glue logic, wrappers and interfaces are connected. The solution hardware is connected to a Synopsys verification environment with USB and DisplayPort test-cases. The verification environment also includes a Power Delivery test suite for Type-C connect/detach and DisplayPort Alternate Mode discovery. A Type-C IC is not included but relevant actions from TCPC hardware and TCPM software are modeled. Designers can insert their own or vendor provided models for the particular Type-C IC they use in their design.

Figure 3: DesignWare USB-C 3.1/DisplayPort TX solution environment

Summary

The pre-configured and integrated DesignWare USB-C 3.1/DisplayPort solution includes all controllers, PHYs, glue logic, wrappers, interconnects, verification IP and test cases required for a USB Type-C implementation that supports DisplayPort Alternate Mode. The solution reduces IP configuration, integration and verification efforts and enables the SoC to meet time-to-market needs while minimizing external (to SoC) components and BoM costs.