Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
Upgrade Your SoC Design to USB4
Morten Christensen, Technical Marketing Manager, Synopsys
Introduction
USB4? is a new standard of connectivity by the USB Implementers Forum (USB-IF). USB4 supports multiple high-speed interface protocols, including USB4, DisplayPort, PCI Express, and Thunderbolt 3 for efficient data transfer and simultaneous delivery of data, power, and high-resolution video through a single USB Type-C cable. USB4 offers up to 40Gbps, which is twice that of the preceding USB 3.2 Gen 2x2 standard. This article provides a brief overview of the new, complex USB4 standard, including the cables and connectors and System-on-Chip (SoC) building blocks. For more details on the standard, download Synopsys white paper, USB4: User Expectations Drive Design Complexity, or the from the USB-IF.
USB4 Cables and Connectors
USB4 can use the same passive Type-C to Type-C cables as USB 3.2, but the cable lengths may differ. While USB 3.2 supports SuperSpeed 5 Gbps for up to 2m cable length, the same cable supports USB4 at 20 Gbps. USB 3.2 supports SuperSpeed 10 Gbps and SuperSpeed 20 Gbps for up to 1m cable, and a 1m cable also supports USB4 20 Gbps. Reducing the cable length to 0.8m enables USB4 40 Gbps support. Therefore, we expect that the USB 3.2 1m cables will be phased out and replaced with 0.8m cables using the new USB4 logo. These 0.8m cables will work for both USB 3.2 and USB4, in addition to DisplayPort Alternate Mode.
Cable lengths longer than 0.8m for USB4 40 Gbps, or 2m for USB4 20 Gbps, require active cables. Active cables are complex designs. USB4 marketing guidelines include new port and cable icons to indicate USB4 support.
USB4 Host, Hub, Dock, and Device
The USB4 specification describes the features and capabilities of the different USB4 product types. Figure 1 shows the USB4 Dual Bus System Architecture, where USB 2.0 (for backwards compatibility) is routed separately from USB4. The USB host Downstream Facing Port connects to the USB4 hub, USB dock (not shown in Figure 1) and USB4 device Upstream Facing Port. Additional USB4 hubs, USB4 dock and/or USB4 devices connect just like the standard USB topology and device tree known from USB 2.0 and USB 3.2 specifications.
Figure 1: Connecting USB4 Host, Hub and Device (adapted from source: Figure 2-1)
USB4 Building Blocks
The descriptions of USB4 host, hub, dock and device show that many different building blocks are required to design USB4 products. Synopsys offers a wide range of DesignWare? IP that is required for designing USB4 products.
USB4 PHYs Supporting Lane Usage Multiplexing
DesignWare USB4 PHY IP is available in advanced process nodes for USB4 host, USB4 hub downstream facing port (DFP), USB4 dock DFP, and some USB4 device applications. Synopsys USB4 PHYs can be customized with a Type-C Assist (TCA) digital cross-bar switch for lane usage multiplexing for host applications as shown in Figure 2. A digital cross-bar switch ensures the best possible signal quality, which is vital for 10 Gbps and 20 Gbps data rates. Synopsys is also planning to make the USB4 PHY available in lower-cost process nodes suitable for some USB4 device applications. The USB4 PHY used for DFP on USB4 hosts, hubs and docks must operate in multiple modes: USB4, Thunderbolt3, USB 3.x and DisplayPort TX Alternate mode, as shown in Figure 2.
Figure 2: Complex USB4, USB 3.x, and DisplayPort (DP) Alt Mode lane usage on Type-C connector
Support for DisplayPort 2.0 in USB4 PHYs
DisplayPort 2.0 traffic is not tunneled over USB4 or Thunderbolt because the USB4 specification only defines DisplayPort 1.4a tunneling. Synopsys USB4 PHYs support DisplayPort 1.4 TX Alternate Mode and can optionally be customized to support DisplayPort 2.0 TX according to the newly announced DisplayPort 2.0 Alternate Mode specification. When customized to support DisplayPort 2.0 TX, Synopsys¡¯ USB4 PHY supports UHBR10, UHBR13.5 and UHBR20 data rates. Four lanes of UHBR20 provide 80 Gbps raw data rate, capable of supporting 8K or even 16k monitors and TVs, high refresh rate gaming, advanced AR/VR, and other advanced display applications.
USB4 Device Router for AI Acceleration
Synopsys offers DesignWare? USB4 Device Router IP, initially targeting (Artificial Intelligence) AI accelerators for edge and mass storage applications. How each AI accelerator functions with associated local compute and memory is dependent on the specific implementation, but one possible example is shown in Figure 3. In USB4 mode, this AI accelerator uses USB4 to connect to a PCIe 4.0 embedded endpoint using tunneled PCIe. This mode enables the AI accelerator to take advantage of a low latency direct memory access (DMA) connection to the host system memory. In USB 3.x mode, this AI accelerator connects to the USB host using either legacy USB streaming (isochronous) or bulk traffic. Figure 3 also shows a customized USB4 PHY that supports PCIe 4.0. Integrating a customized USB4 PHY allows the AI accelerator to be mounted on a PCB in an embedded host or mounted on a PCIe expansion card.
Figure 3: AI accelerators for edge and mass storage use USB4 router IP support new functionality
Complete SoC Designs with Additional USB4 Building Blocks
In addition to the DesignWare USB4 PHY IP and USB4 device router, Synopsys offers xHCI Enhanced SuperSpeed Controller IP for use in USB4 host, USB4 hub and USB4 dock products. Additionally, Synopsys offers USB 2.0 and USB 3.2 device controller IP for use in USB4 dock and USB4 device products, as well as USB 2.0 and USB 3.2 PHY IP for legacy USB ports in USB4 dock and USB4 device products. For display applications, Synopsys offers DisplayPort 1.4 TX (source) controller IP, with high definition content protection (HDCP) using the Synopsys HDCP 2.3 Embedded Security Module. This IP combination can be used for USB4 host, USB4 dock and USB4 device products.
Synopsys also offers DesignWare USB/DisplayPort 1.4 PHY IP that can be used with legacy DisplayPort connectors for USB4 dock and USB4 device products. Designers wanting to differentiate their USB4 dock design can integrate Synopsys HDMI controller and PHY IP with HDCP 2.3 ESM security IP for legacy HDMI port(s) on a USB4 dock or USB4 device. Synopsys DesignWare PCIe Controller (PCIe Root Complex) IP for USB4 host, PCIe switch for USB4 hubs, USB4 docks and complex USB4 devices, in addition to PCIe device controller (PCIe embedded endpoint) can be used for USB4 dock and USB4 device products.
Summary
USB4 complexity is driven by user expectations, and consumers will expect USB4 products to support USB, Thunderbolt, and DisplayPort operating modes and products that exist today. Well-designed USB4 products will also support future products, if designed to existing specifications. Only the future will show if the USB4 specification as published in 2019 is the last USB specification, if there will be a USB4 speed bump, and/or if designers will have to confront USB5 sometime in the future. Regardless, USB4 product designs that meet user expectations that ¡°USB just works¡± will make USB4 a success.
As a major contributor to USB technology and standards, Synopsys employees have contributed to almost every published USB standard. Synopsys is the world¡¯s most preferred and most widely used supplier of USB IP for all USB standards, from USB 1.1 to USB4. Contact Synopsys for further information on how we can help your next design support the latest USB4 specification, or kickstart projects that need PCIe, USB, and/or DisplayPort with HDCP IP support.
Additional USB4 Resources:
- White paper: USB4: User Expectations Drive Design Complexity
- Synopsys DesignWare USB4 IP website: /usb4
- USB4 specification:
- USB4 Developer Days presentations: