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IP Integration with Less Effort, Lower Risk, and Faster Time-to-Market
By Johannes Stahl, Director of Product Marketing for Virtual Prototyping, Synopsys
With the increase in SoC hardware and software complexity, it¡¯s no longer enough to provide just IP blocks. Both hardware engineers and software developers need more from their IP providers to help them meet their schedules. Hardware engineers need ¡°known good¡± IP configurations that can be easily modified to explore design tradeoffs. Software developers need proven targets so that they can start work on software development, bring-up, debug, and test earlier in the product development process. Customized IP subsystems that fit right into the target SoCs can help to significantly reduce overall SoC development cost.
With the IP Accelerated initiative, Synopsys is delivering more than silicon-proven IP blocks, going beyond what is traditionally expected from IP suppliers. Synopsys is helping designers achieve successful IP integration with less effort, lower risk, and faster time-to-market with DesignWare? IP Prototyping Kits, DesignWare IP Virtual Development Kits, and customized IP subsystems, each of which accelerates prototyping, software development and integration of IP into SoCs (Figure 1).
Figure 1: IP Accelerated initiative includes the elements both software developers and hardware engineers need to speed SoC design and software development
Faster SoC Bring-up and Configuration for Hardware Designers
The DesignWare IP Prototyping Kits include a ready-to-use, out-of-the box reference design that is pre-loaded with a known good configuration of the IP and SoC integration logic.
The proven reference design for the DesignWare IP, included in the IP Prototyping Kits, enables hardware designers to be instantly productive, accelerate the integration of IP into their target SoC, and optimize the IP configuration. Designers can modify the standard IP configuration for their target application through a fast iteration flow consisting of Synopsys¡¯ coreConsultant IP configuration tool, Synopsys¡¯ ProtoCompiler DX synthesis and debug tool, and compilation scripts.
The complete hardware kit consists of a HAPS-DX FPGA-based prototyping system, a PHY daughter board, simulation testbenches and the ARC Software Development Platform (SDP) as shown in Figure 2. The ARC SDP consists of a CPU card mounted on an ARC SDP mainboard and the associated software stack of a pre-built operating system, drivers, and examples. The ARC SDP comes with a rich set of I/Os including an HDMI connector that designers can use to connect the monitor and a USB connector for the keyboard/mouse used to program and operate the IP Prototyping Kit.
Figure 2: IP Prototyping Kits offer a ready-to-use, out-of-the-box reference design and pre-loaded software stack
Start Software Development Earlier with IP Software Development Kits
The IP Accelerated initiative offers two proven targets to software developers for early software development, bring-up, debug and test: IP Prototyping Kits for developers who prefer a physical target and IP Virtual Development Kits (IP VDKs) for developers who prefer a virtual target. Both kits enable developers to get up and running instantly, as shown in Figure 3:
- Out-of-the-box support for a Linux software stack ensures that software developers can focus on the IP-specific software (e.g., drivers, bootcode, firmware)
- Proven reference physical or virtual targets plus into existing software tool chains and interface with the most popular embedded software debuggers
- Unparalleled debug and control across the entire platform
- Easily extendible to full SoC target
Figure 3: Proven software development kits for early software bring-up, debug, and test
DesignWare IP Prototyping Kits: Physical Targets for Software Developers
In addition to accelerating hardware development, the IP Prototyping Kits accelerate software integration and validation of Synopsys DesignWare IP by enabling software development, validation, code porting, software debug, and analysis. The IP Prototyping Kits offer this capability with a physical target ¨C an FPGA-based hardware platform--for teams that prefer hardware and FPGA-based prototyping. The kits provide embedded software engineers with an ideal, ready-to-use solution for efficient coding. The benefit of an out-of-the-box solution for hardware developers that takes out months out of the IP exploration schedule directly translates into the same benefit for the software developer that now can receive the configured physical target months earlier in their schedule.
DesignWare IP VDKs: Virtual Targets for Software Developers
As shown in Figure 4, the DesignWare IP VDKs include the elements that software developers need to start early software bring-up, debug, and test concurrently with SoC development. To ensure that software developers are up and running instantly and can focus on their critical deliverables, the kits provide:
- A reference virtual prototype that includes a configurable model of DesignWare IP and a model of a multi-core ARM? Cortex?-A57 Versatile? Express board
- Out-of-the-box support for Linaro Linux OS with reference drivers for DesignWare IP
- Eclipse-based tools for easy integration with software debuggers
- Unparalleled, non-intrusive debug control and visibility
Figure 4: Elements included in DesignWare IP Virtual Development Kits
IP VDKs dramatically boost software developer productivity with superior debug visibility and are easy to deploy among Windows or Linux OS PCs. In addition, the DesignWare IP software model can be optimized for any target or application mode, based on the operating mode of the ARMv8 processor, either 32-bit or 64-bit.
In addition to enabling software development before SoC hardware availability, the IP VDKs offer unique visibility into the internal state of the platform through the virtual prototype. Each individual piece of information can be combined to create unique system-wide views to help debug and analyze software issues and optimize the software in the context of the actual IP subsystem. IP VDKs also offer an advantage in their capability to control the execution of the software in a deterministic way, and to enable non-intrusive debugging.
Customized IP Subsystems to Reduce Integration Cost
As SoCs move up the complexity chain, system architects and managers are looking to IP vendors to play a bigger role in their IP integration efforts. With extensive knowledge in IP integration, Synopsys experts can assist designers in customizing IP subsystems for specific application requirements as well as with integrating the subsystem into their SoC. To reduce cost and accelerate time-to-market, customers can leverage Synopsys¡¯ IP expertise to obtain pre-validated, fully integrated subsystems, reducing the overall effort and risk to assemble and integrate the IP. By utilizing Synopsys¡¯ subsystem integration experts, designers can focus on their SoC differentiation and not on developing or integrating standards-based IP.
IP Accelerated: Redefining the IP Paradigm
With IP Accelerated, Synopsys is redefining what customers can expect from their IP partners. By going beyond providing a broad portfolio of silicon-proven IP, Synopsys allows customers to reduce the cost of configuring and integrating the IP for their specific SoC projects as well as accelerating the software schedules associated with a shipping a complete solution to their OEM customers.