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Complexity of Interface Protocols

Interface protocols start out simply, handling off-chip communication for SoCs. As more companies get involved in the specifications, each company adds features to address their market segments. Each new version of the protocol specifications offers new features and increased speed. Many times the protocols have to be overhauled to work at higher speeds and improve performance. Along the way there are inevitable issues, so the standards include ECOs for certain use cases¡ª all the while maintaining backwards compatibility.

When the protocols were simple, every company had in-house experts, but soon companies realized these resources could be better used to differentiate their chips and they could just purchase interface IP from third-party IP vendors like Synopsys. The vendors create feature-rich products that meet all aspects of the specifications and also offer a wide range of configuration options. Configuration options are very helpful but require effort to learn and understand the tradeoffs of area vs. speed vs. power.

While some designers prefer to buy controllers and PHYs separately, many are asking their vendors to provide pre-verified interface IP subsystems (Figure 1) to reduce their effort and time to market. Basically, designers want to buy the complete interface. Synopsys has leveraged our IP design teams¡¯ expertise to create DesignWare Interface IP Subsystems.

Interface IP Subsystems help designers because SoCs are far more complex and time-to-market pressure is intense. Protocols run at higher speeds, are used in everything from small consumer devices to server applications, and must be backward-compatible with multiple previous generations. SoC designers are creating more complex architectures to accommodate ever increasing complexity, speed, bandwidth and memory requirements. SoC designers now struggle to understand the individual requirements of multiple IP blocks and to create an optimized configuration that will enable their applications to run most efficiently.

SoC designers require a complete IP interface ready for their SoC, including analysis and verification, or an interface IP subsystem that can be quickly integrated into the SoC to meet their time to market requirements (Figure 2). DesignWare Interface IP Subsystems fulfill these requirements and more.

IP Suppliers as Subsystem Suppliers

Because IP suppliers work with multiple customers, IP suppliers are better suited than individual SoC designers for the task of building and configuring IP subsystems. In addition, each new project benefits from the IP supplier¡¯s experience from previous projects, taking the IP reuse paradigm to the subsystem level. IP suppliers should offer services ranging from the integration of the controller and PHY, through integration of multiple protocols with common PHYs, all the way to complete subsystems that also include the software stack.

Integrating IP from multiple IP suppliers can be more complex. For example, when connecting IP using a controller and PHY from different suppliers, often the interface between them is not designed to a standard. Even when it is, there¡¯s no way of performing interoperability testing between the controller and PHY, there is no simple way to confirm the connection is correct, nor is there a way to make sure all the signals have the correct functionality. Even if both IP suppliers test the interfaces thoroughly, if they have interpreted the specifications differently, the interfaces will behave differently. Also, sometimes the specification does not indicate where in the controller or in the PHY that certain functionality should be performed. This could lead to both IP suppliers providing the functionality¡ª or neither. Using an IP subsystem from an experienced IP supplier can help designers avoid these issues because they will have studied the specifications and supported customers through these kinds of issues many times. The IP teams have seen all of these issues when supporting customers with integration of IP and have put specific tests and configuration options in the Interface IP Subsystems to handle the limitations of integrating IPs from different IP vendors.

Performance Analysis

With high-performance interfaces offering myriad configurations, narrowing down the options to the exact configuration required for a particular application can be challenging. IP suppliers should assist the SoC designer with selecting the optimal configuration of the IP, usually through the use of custom data flow tools. For example, DDR traffic pattern analysis is critical to the organization of memories and arbitration of different masters. Often DDR masters can have varying and contradicting requirements. The Interface IP Subsystem team can use tools such as Synopsys DDR Explorer to achieve the required system performance without starvation (Figure 3). Part of the traffic pattern analysis includes address mapping optimization to reduce page misses, which can improve DDR performance by as much as 20 percent. In addition, by closely analyzing the clock frequency, the IP supplier can enable higher bandwidth at lower frequency, which can ultimately reduce the cost of memory devices and cut power.

SoC Integration

Once the configurations have been confirmed, the IP supplier can focus on integration of the IP into the design. The SoC designer needs to be able to integrate the IP confidently while dealing with multiple configurations, clock domains, power domains, and still meet timing and performance requirements. Typically, integrating IP requires knowledge of multiple interfaces and options from the SoC to the controller IP and the PHY IP. Using IP subsystem model, all the SoC designer needs to do is provide the IP supplier with performance requirements and details about the SoC design. The IP supplier can then modify the subsystem to meet the SoC requirements. The IP supplier should include not only the configuration of the IP subsystem but also design functionality such as clock structures, reset requirements, low power functionality and the SoC¡¯s design-for-test (DFT) requirements.

IP Subsystem Verification

Connecting and configuring the IP to create a subsystem is important, but it is equally important to test and verify this new subsystem in the context of the IP and in the context of the SoC. There are several phases of this testing that the IP provider must consider to meet the requirements of the SoC. For example, for many customers the initial phase upon receiving an IP subsystem is to first verify that it functions as specified. Next will be the integration of the IP subsystem into the SoC and verifying interconnectivity, performance tests and for high speed interfaces signal integrity testing (Figure 4). To facilitate these tests, the IP supplier and SoC designer will create an extensive verification plan that clearly outlines and defines all tests with coverage including interconnectivity, interoperability, end-to-end data integrity tests, protocol checks and so on. In this way the SoC designer can easily understand and know which tests they need to port to the SoC level. Additionally, if the IP subsystem includes IP from two different suppliers, the subsystems include additional tests that can identify known interoperability issues and can add assertions for specific events. By performing integrated testing, the IP provider will help designers reduce integration and verification time from several weeks to a few days.

For example, a high-speed interface IP subsystem, such as DDR, typically needs to achieve high levels of performance. At such high data rates a complete system design approach should be undertaken rather than a more limited focus on just the SoC design or package design. Consideration should be given to:

• PCB design, e.g. PCB construction, stack-up, routing, crosstalk, transmission lines and termination
• Packaging, e.g. package type and routing, power integrity, core power and ground
• Power delivery, e.g. power delivery network including considerations for generation of clean supplies including reference and PLL voltages
• Timing budgets

For high-performance DDR interfaces to be successful, extra care must be taken during the design and layout phase to make sure all steps are taken to create a well-controlled signal integrity and power integrity environment. Creating such environments with tight skew control, optimum termination values, and clean reference levels requires a specific skill set and experience that can be provided to ensure signal and power integrity targets can be met for a successful design. 

Implementation Analysis

Analyzing the design¡¯s performance and implementation is the next critical step. This analysis should be done by scrutinizing the clock domain crossing (CDC), linting the RTL code, synthesizing the design, and completing timing checks to make sure the design will function in the required technology node. Of course, the IP provider should be knowledgeable in the protocol, the IP and the configuration that will make the design meet the performance requirements. The supplier will execute all of the implementation tasks needed to complete the IP subsystem deliverables, simplifying the effort for the SoC designer to drop the subsystem into their SoC.

Summary

In the most efficient SoC design processes, semiconductor companies design their own differentiated logic and features, acquire high-quality third-party IP for standard interfaces, configure and optimize the IP for the SoC, and integrate all blocks into the SoC infrastructure of clocks, voltage supplies, on-chip buffer memories or registers, and test circuits. The SoC design team defines and drives the SoC-specific implementation details and hence imposes certain requirements on how the IP can be integrated. By providing a fully customized, analyzed and tested IP subsystem, IP suppliers like Synopsys can play a significant role in enabling the SoC design team to focus on the development of differentiated blocks and help them reduce standard IP interface integration time and effort to meet time-to-market goals. DesignWare Interface IP Subsystems fulfill the promise of delivering interface IP and SoC knowledge in one package and easing the pressure on the SoC designer.

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