Full chip ILT mask synthesis for advanced memory manufacturing
27 February 2023 ? 10:30 AM - 10:50 AM PST | Convention Center, Room 210A
Curvilinear mask handling in OPC flow
27 February 2023 ? 11:10 AM - 11:30 AM PST | Convention Center, Room 210A
Improving OPC modeling accuracy with rigorous and compact modeling deformation effects in photoresists
27 February 2023 ? 3:40 PM - 4:00 PM PST | Convention Center, Room 210A
Evaluation of field stitching optimization for robust manufacturing with high-NA EUVL
27 February 2023 ? 4:40 PM - 5:00 PM PST | Convention Center, Room 210A
Verification methods for curvilinear and real-curve geometries
28 February 2023 ? 3:10 PM - 3:40 PM PST | Convention Center, Room 210A
Absorber material deficiency impact on a stochastically patterned wafer analyzed with a clustered model
1 March 2023 ? 8:40 AM - 9:00 AM PST | Convention Center, Grand Ballroom 220A
High accuracy OPC modeling for new EUV low-K1 mask technology options
1 March 2023 ? 9:00 AM - 9:20 AM PST | Convention Center, Room 210A
Modeling accuracy and TAT improvements for next generation mask error correction
1 March 2023 ? 9:20 AM - 9:40 AM PST | Convention Center, Room 210A
Computational patterning and process variation impact on photonics devices
1 March 2023 ? 10:10 AM - 10:30 AM PST | Convention Center, Room 210C
Electrical analysis of a stochastically simulated 2 nm node electrical test structure
1 March 2023 ? 2:20 PM - 2:40 PM PST | Convention Center, Room 210A
Scalable hierarchy extraction of repeating structures to enhance full chip mask synthesis
1 March 2023 ? 2:40 PM - 3:00 PM PST | Convention Center, Room 210A
A Synopsys TCAD-based workflow to support technology evaluation at 3nm and beyond
1 March 2023 ? 4:10 PM - 4:30 PM PST | Convention Center, Room 210A
Process optimization for next generation high-NA EUV patterning by computational lithography techniques
2 March 2023 ? 9:20 AM - 9:40 AM PST | Convention Center, Grand Ballroom 220A
Machine learning applications on 3nm node technology and designs for improving block-level PPA
2 March 2023 ? 11:40 AM - 12:00 PM PST | Convention Center, Room 210A
Automatic generation of representative and diversified pattern samples from a full chip layout
2 March 2023 ? 12:00 PM - 12:20 PM PST | Convention Center, Room 210A
Machine learning based inverse lithography technology for an advanced DRAM contact layer
2 March 2023 ? 2:30 PM - 2:50 PM PST | Convention Center, Room 210A
Poster
Mask absorber material or tone and process impact on resist line edge roughness
1 March 2023 ? 5:30 PM - 7:00 PM PST | Convention Center, Hall 2
Courses
Machine Learning for Lithography
26 February 2023 ? 8:30 AM - 5:30 PM PST
