91³Ô¹ÏÍø

Elevate and Maximize Your Design Signoff

 

Join us at this year¡¯s Synopsys Signoff SIG (Special Interest Group) event. 

Signoff is a critical quality control checkpoint in the chip development process, but design complexity and advance process nodes are pushing the boundaries of what is expected of signoff solutions. Meeting these scaling challenges is becoming more difficult. At this year¡¯s Synopsys Signoff SIG event, we¡¯ll explore how signoff can help meet these scalability challenges. We¡¯ll hear from several industry-leading companies how they are using the latest technology advances in timing, power, extraction, and eco to realize the full PPA potential of their designs with the fastest path to design closure.


Keynote: Signoff in the Era of System Design

 

Complexity is pushing the limits of single process nodes and what monolithic designs can achieve. A multi-die approach offers much needed design flexibility. This approach, however, also comes with challenges that need to be overcome. As a leader in multi-die systems, Arm will address specific challenges related to system-level signoff including thermal, clock jitter, power, timing, workload and pre-silicon to post-silicon estimation. The session will then outline the signoff solutions that can help alleviate these challenges to reach signoff closure in this era of system design.

Reiner Genevriere

VP of Engineering

Synopsys

Mamta Bansal.jpg

Mamta Bansal

Sr. Dir 91³Ô¹ÏÍø Engineering

Arm

Agenda


Thu. October 03, 2024
11:30 - 12:15 PM PDT
Registration Check in & Lunch
Keynote
Thu. October 03, 2024
12:15 - 01:15 PM PDT
Signoff in the Era of System Design
  • Mamta Bansal, Arm
  • Reiner Genevriere, Synopsys
Technical Session
Thu. October 03, 2024
01:15 - 01:40 PM PDT
Power Signoff with Synopsys PrimePower Delay Shift and RTL FSDB
  • Dan Stasiak, Qualcomm
Technical Session
Thu. October 03, 2024
01:40 - 02:05 PM PDT
Utilizing Synopsys PrimePower and ZeBu Empower to Reach Power Signoff
  • Masood Syed - Meta
Technical Session
Thu. October 03, 2024
02:05 - 02:40 PM PDT
Socionext Full-chip Over Billion Gate Design Closure Flow using PrimeTime HyperGrid, HyperScale, and PrimeClosure
  • Akihiro Nakamura, Socionext
Technical Session
Thu. October 03, 2024
02:40 - 03:05 PM PDT
Acceleration of Timing Impact Assessment with Machine Learning Across the Design Cycle
  • Srinivas Bodapati, Intel
Technical Session
Thu. October 03, 2024
03:15 - 03:40 PM PDT
Scalable and High Performance Clock Jitter and Integrity Analysis for High Frequency Designs
  • Amirali Shayan, Qualcomm
Technical Session
Thu. October 03, 2024
03:40 - 04:05 AM PDT
Boosting Productivity and Precision: Leveraging StarRC for Accurate Results and Efficient Debugging
  • Pallavi Manjunath, Google
Thu. October 03, 2024
04:05 - 05:00 PM PDT
Networking Reception

Location Details

Santa Clara Marriott

2700 Mission College Blvd, Santa Clara, CA 95054

California Ballroom

Follow signs to the check-in and badge pick up.  Please bring a photo ID for check-in. 

 

Please note this event is co-located with the Synopsys VC Formal SIG event.