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Why Attend?
Synopsys is the world¡¯s leading provider of solutions for designing and verifying advanced silicon chips. Join us at DVCon US 2025 to learn how we help customers optimize chips for power, performance, and cost, cutting months off their project schedules.
Keynote
AI-driven Era of Pervasive Intelligence Necessitates New Design, Optimization and Verification Strategies
Date & Time: Tuesday, February 25, 2025 | 1:30 - 2:30 PM
Artificial Intelligence (AI) has transfixed the attention of the world and is infusing the electronics landscape from cloud-to-edge, including HPC, data center, PCs, smartphones, automotive, robots and many more devices. Architects and design teams are creatively producing AI engines that meet specific AI model and end-market application requirements. This new era of workload-specific AI accelerators necessitates new design, optimization, and verification strategies that must be performed in the context of the power and performance requirements of the end-market application. This new generation of customized chips driven by software workloads requires innovative, advanced and AI-assisted methodologies to ensure successful tapeouts in an increasingly complex, cost-driven, and fast time to value (TTV) environment. Hear from Synopsys and Microsoft how industry leaders are addressing these challenges from silicon to system and paving the way for further advancements in this new AI-driven era of pervasive intelligence.?
Synopsys Sessions
Workshop: Moving Application-level Power Optimization to Pre-silicon with Advanced Hybrid Emulation and Power Exploration Technologies
Presenters: Leonard Drucker (Synopsys), Malte Doerper (Synopsys), Ritesh Goel (Synopsys)
Date & Time: Monday, February 24th / Time: 1:30PM - 3:00PM
Abstract:
As the semiconductor industry is experiencing an explosion in design size and complexity, it is accompanied by a need to deliver software readiness when the silicon is back in the lab. One of the key targets for software readiness is the adherence to a power budget with real software applications stressing the hardware design. There are 2 key elements to validating power budgets in pre silicon ¨C performance of the model and the ability to execute a full software stack. Combining a fast virtual prototype of the CPU sub-system with the RTL of the remaining SoC running on an emulator typically produces a 10x speed-up over fully-RTL emulation setups. Recent advances in both virtual prototyping and emulation now yield another leap in hybrid performance, which enables pre-silicon execution of entire software stack. Similarly, the power analysis engine needs to become efficient to be able to handle these large workloads and be able to address requirements of peak power, average power and leakage power. In this workshop, we will first review the latest state-of-the-art of hybrid emulation technologies and use-cases. We will then illustrate the application of hybrid emulation for pre-silicon power optimization.
Tutorial: Next-Gen Verification Technologies for Processor-Based Systems
Presenters: Aimee Sutton (Synopsys), Ravindra Aneja (Synopsys), Xiaolin Chen (Synopsys), Nilabja Chattopadhyay (Amazon), Jevin Saju John (Synopsys), Bjoern Hartmann (Synopsys)
Date & Time: Thursday, February 27th / Time: 9:00AM ¨C 12:30PM
Abstract:
Today¡¯s complex processor-based systems enable technological advances in many market segments, such as AI, high performance computing, and automotive. However, verification of these systems introduces new challenges, spanning architectural verification of a custom RISC-V processor to memory coherency in a system containing thousands of Arm or RISC-V cores. As the complexity of the design increases, so does the need for new tools and methods beyond simulation and UVM testbenches. ?
In this tutorial, we will focus on RISC-V processors and present next-generation verification techniques that span the verification journey from a single RISC-V processor to complex systems with many RISC-V cores. ?
To accommodate the flexible and evolving nature of the RISC-V ISA, as well as privilege mode features, out-of-order pipelines, interrupts and debug mode, RISC-V processor verification requires innovation in stimulus generation, comparison, and checking. We will cover dynamic and formal approaches to verifying RISC-V cores, with topics including, but not limited to: ISA compliance verification and functional coverage, datapath validation, functional verification of critical blocks, and security verification. ?
Multi-core designs introduce a new set of challenges, such as ensuring fair access to shared resources and cache and memory coherence. This tutorial will present solutions designed to address these issues and prevent costly bug escapes to silicon. ?
The size of multi-core designs and multi-processor SoCs means that a simulation-only verification strategy is impractical. Hardware-assisted verification becomes essential to ensuring correct operation in the multi-core designs of today and the future. This tutorial will demonstrate how Synopsys¡¯ next-generation processor verification tools and techniques combine with HAV platforms to create a powerful and effective solution. ?
Whether you are designers or verification engineers of these complex processor-based systems, you will walk away with new ideas on how to improve your verification flow by embracing some of these next generation solutions.
Technical Session 4: Performance Verification for AI Heterogenous Multicore Systems using Portable Stimuli Standard
Date & Time: Tuesday, February 25th / Time: 3:00PM ¨C 5:00PM
Technical Session 10: Leverage Real USB Devices for USB Host DUT Verification
Date & Time: Wednesday, February 26th / Time: 3:30PM ¨C 5:00PM
Exhibit Booth
Visit Synopsys Booth #116
Stop by to see how we deliver comprehensive verification solutions spanning the complete design cycle, including simulation, emulation, advanced debug, static/formal verification, FPGA-based prototyping and virtual prototyping.
