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Synopsys Advances Automotive Security with ISO/SAE 21434 Cybersecurity Certified ARC HS
You can now accelerate the security qualification of your automotive chips with Synopsys? ARC? HS Functional Safety Processor IP, the industry¡¯s first IP product to achieve ISO/SAE 21434 cybersecurity certification. This IP meets stringent automotive regulatory requirements designed to protect connected vehicles from malicious cyberattacks. To ensure all Synopsys IP products are developed with a security-first mindset throughout every phase of the product development lifecycle, our interface, security, and processor IP development process are also ISO/SAE 21434 certified.
Maximum Performance for Embedded Applications
The latest additions to the ARC? HS family, the 32-bit ARC HS5x and 64-bit HS6x processors, are based on the new ARCv3 instruction set architecture (ISA). The previous generation HS processors, based on the efficient ARCv2 instruction set architecture (ISA), include the HS3x, HS4x, and DSP-enhanced HS4xD processors. All HS processors support closely coupled memories (CCMs), which enable single-cycles access to instructions and data.
HS processors are optimized for GHz+ operating speeds with minimum area and power consumption, making them ideally suited for embedded applications with very high-performance requirements. The HS processors are available in single-core, dual-core and quad-core configurations.
The ARC HS processors are supported by a broad ecosystem of commercial and open-source tools, operating systems, and middleware. This includes offerings from leading industry vendors who are members of the ARC Access Program as well as a comprehensive suite of free and open source software available through the embARC.org website.
Products
ARC HS34/HS36/HS38
The ARC HS34/HS36/HS38 processors are ideal for embedded applications that require high performance efficiency. They feature an optimized 10-stage pipeline, L1 coherency, and up to 8 MB of L2 cache, ensuring efficient software development.
ARC HS44/HS46/HS48
The ARC HS44/HS46/HS48 processors feature a superscalar architecture designed for high-performance embedded applications. They offer a high-speed, dual-issue pipeline, full MMU with a 40-bit address, and come in single-, dual-, and quad-core versions.
ARC HS45D/HS47D
The ARC HS45D/HS47D processors combine dual-issue, 32-bit RISC and DSP architecture, making them ideal for high-performance embedded applications requiring signal processing. They feature over 150 DSP instructions and offer easy DSP programming support.
ARC HS46FS/HS47DFS/HS48FS
The ARC HS46FS/HS47DFS/HS48FS processors are dual-issue solutions designed for high-performance automotive applications. They feature error detection and correction code and are available in single-, dual-, and quad-core implementations.
ARC HS56/HS57D/HS58
The ARC HS56/HS57D/HS58 processors feature a 32-bit superscalar architecture designed for high-end embedded applications. They include a 32-bit ALU and core registers, support a 32-bit virtual and 40-bit physical address space, and are scalable up to a 12-core coherent cluster.
ARC HS66/HS68
The ARC HS66/HS68 processors feature a superscalar 64-bit architecture that supports 52-bit physical and 64-bit virtual addresses. They include a 64-bit pipeline and register set, an advanced FPU with 128-bit SIMD, and are scalable up to a 12-core coherent cluster.
ARC Software Development Platforms:
- ARC HS Development Kits
- ARC AXS103 Software Development Platform (complete, standalone platform for software development, debugging, and profiling)
ARC Development Tools and Software:
- MetaWare Development Toolkit (compilers, debugger, and simulator)
- GNU Tools (compiler, debugger, utilities) & ARC Linux OS
- MQX RTOS
- embARC Open Software Platform (comprehensive suite of free and open source software)
- ARC Access Program (portfolio of 3rd party tools, operating systems, and middleware)
Licensable Options
Features
ARC processors are optimized to deliver the best PPA efficiency in the industry for embedded SoCs.
- Harvard architecture for higher performance through simultaneous instruction and data memory access
- High-speed pipeline designed for maximum power efficiency
- 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density
ARC processors are highly configurable, allowing designers to optimize the performance, power, and area of each processor instance on their SoC.
- Add or omit hardware features to optimize the core for your target application - no wasted gates
- The ARChitect wizard enables drag-and-drop configuration of the core
ARC Processors EXtension (APEX) technology enables users to customize their processor implementation.
- Add user-defined instructions to accelerate software execution and reduce code size, reducing energy consumption and memory requirements
- Tightly couple memories and peripherals to the processors to eliminate the need for additional bus infrastructure, reducing area and latency and increasing system-level performance