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The Synopsys ARC? HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where high-performance and high clock speed are required. The processors can be clocked at up to 1.8 GHz in 16FFC processes (worst case, single core, base configuration) and offer outstanding performance delivering 3.0 DMIPS/MHz and 6.16 CoreMark/MHz with a small area footprint and low power consumption.

The ARC HS66 and HS68 processors are based on the advanced ARCv3 instruction set architecture (ISA) and pipeline, which provides leadership power efficiency and code density. The processors feature a 52-bit physical address space and can directly address memories up to 4.5 Petabytes(4.5x10¹⁵) in size. For applications requiring higher performance, Multicore Processor (MP) versions of the HS66 and HS68 are available with support for up to 12 HS CPU cores and up to 16 hardware accelerators in the processor cluster.

The ARC HS66 features level 1 (L1) instruction and data cache and closely coupled memory (CCM) and is optimized for use in high-performance real-time embedded applications. The HS68 is designed for use in applications running Linux or SMP Linux. The HS68 has all the features of the HS66 plus support for L2 cache up to 64 MB and a Memory Management Unit (MMU).

To maximize PPA of ARC HS6x-based processor designs, a Fusion QuickStart Implementation Kit (QIK) that includes tool scripts, a baseline floorplan, design constraints and documentation, is available.

Synopsys ARC HS66 and HS68 Block Diagram

Synopsys ARC HS66 and HS68 Processors Datasheet