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Highlights

• SystemVerilog and Verilog testbench
• Native UVM support
• Runs natively on all major simulators
• Protocol-aware debug
• Built-in verification plan and coverage
• Built-in protocol checks
• Error injection
• HTML based documentation
• Source code visibility

Key Features

• Configurable Baud Rate Divisor
• Configurable data-width with 5, 6, 7, 8 and 9-bits
• Fractional Baud Rate Divisor
• Supports full-duplex
• Supports line break generation and detection
• Provides hardware, or out-band, flow control
• Provides software, or in-band, flow control
• Supports 1 and 2 stop bits, parity (even, odd)
• Provides receiver FIFO with configurable depth