Cloud native EDA tools & pre-optimized hardware platforms
Synopsys Verification IP (VIP) for JTAG provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of JTAG based designs. VIP JTAG is integrated with Verdi Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, graphical view of memory operations. VIP JTAG is written entirely in SystemVerilog to run natively in any IEEE SystemVerilog compliant simulator for optimum performance. Testbench development is accelerated with the assistance of built-in verification plans, example tests and a sequence collection.