Cloud native EDA tools & pre-optimized hardware platforms
Synopsys Verification IP (VIP) for CPRI provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of CPRI based designs.
VIP, based on its next generation architecture and implemented in native System Verilog/UVM, runs natively on all major simulators. VIP can be integrated, configured, and customized with minimal effort. Testbench development is accelerated with built-in verification plan and functional coverage.
Contact the VIP Team