Cloud native EDA tools & pre-optimized hardware platforms
Synopsys Verification IP (VIP) for Interlaken provides a comprehensive set of protocol, methodology, verification, and ease-of-use features, enabling users to achieve accelerated verification closure of Interlaken designs. VIP, based on its next-generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VIP can be integrated, configured, and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.