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RTL to Signoff Power Analysis
The Synopsys PrimePower product family enables accurate power analysis for block-level and full-chip designs starting from RTL, through the different stages of implementation, and leading to power signoff.
PrimePower RTL power estimation leverages the Predictive Engine from Synopsys' RTL Architect? product to provide RTL designers with fast, scalable, and accurate power estimation for early analysis of RTL blocks, subsystems, and full-SoCs. PrimePower RTL enables designers to analyze, explore, and optimize their RTL with confidence, improving power, energy efficiency, and shortening the design cycle.
During implementation and signoff, PrimePower provides accurate gate-level power analysis reports for SoC designers to make timely design optimizations and achieve power targets. Supported power analysis includes average power, peak power, glitch power, clock network power, dynamic and leakage power, and multi-voltage power; with activity from RTL and gate-level vectors from simulation, emulation, and vectorless analysis. By closely integrating with PrimeTime, the golden industry standard for timing and signal integrity analysis and signoff, PrimePower expands the PrimeTime solution to deliver accurate dynamic and leakage power analysis and signoff for gate-level designs.
Features and Capabilities
PrimePower RTL: RTL Power Estimation
- RTL vectors from simulation and emulation, and vectorless what-if analysis
- RTL average, peak, glitch, clock, dynamic, leakage, and multi-voltage power analysis & reporting
- Clock-gating, memory, data-path, and glitch power exploration and guidance
- Physically-aware, signoff-consistent power estimation results
- Graphical debug and waveform visualization
PrimePower: Gate-level Power Analysis and Golden Power Signoff
- Vectorless average and target power what-if analysis
- Concurrent reading of RTL and gate-level vectors from simulation and emulation
- Gate-level average, peak, glitch, clock, dynamic, leakage, and multi-voltage power analysis & reporting
- Early glitch analysis, peak power analysis, and IR profiling using PrimePower activity delay shifting
- Glitch-aware SAIF file generation for implementation power recovery and ECO signoff
- Efficient IPF, STA, & glitch-aware FSDB file generation for use in Ansys? RedHawk? IR-drop analysis
- Advanced node analysis and signoff including Cell-EM, context-aware leakage, and CCS support
- Graphical debug and waveform visualization
What's New
Your Innovation, Your Community
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