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ESP is a formal equivalence checking tool commonly used for full functional verification of custom designs such as embedded memories, custom macros, standard cells and I/O cell libraries. It is used to ensure that two design representations are functionally equivalent. These designs may be represented as Verilog behavioral model, RTL, Gate, Switch or SPICE or .db netlist views.
Using Symbolic Simulation For SRAM Redundancy Repair Verification
Leveraging Symbolic Simulations For IO Verification
Cell Library Verification Using Symbolic Simulation
Validating Memory Design Scan Chains from Behavioral to Transistor Level
Detecting Electrical Hazards Incurred By Inter-Voltage Domain Crossing In Custom SRAMs
ESP Workshop - Learn how to perform functional equivalence checking using ESP