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For digital library characterization, some of the views are usually provided by the design while others must be derived. For instance, the logic function of a NAND gate could be defined as "!(A & B)." In principle, all other views can be derived from this equation using some additional assumptions and constraints, depending on the technology and design goals. The netlist of combinatorial cells can be generated algorithmically. Starting from the netlist, a layout will be drawn which can be used to extract parasitic capacitances and resistances within the cell. The resulting netlist of transistors and parasitics can be further used to get an abstract description of the cell¡¯s timing, power, and noise behavior.

One way to derive timing and power numbers is through simulation of the transistor netlist. However, one simulation is not enough because the cell¡¯s behavior strongly depends on other factors, such as process, voltage, and temperature (PVT), input wave form, and output load. A common approach is to look at the best and worst PVT conditions. Effectively, this allows you to predict lower and upper bounds of the cell behavior, which are important to ensure the overall functionality of the design. Further, cells must be characterized over a reasonably large range of input edge rates and output load. For example, a cell could be characterized on a two-dimensional grid with variable input edge rate and output load (non-linear delay model). If the grid points are chosen correctly, then the behavior between grid points can be approximated by linear interpolation.

Cell library characterization typically takes cell design extracted as SPICE circuit and SPICE technology models. The characterization tool analyzes this information to:

1. Acquire the functionality of the cell
2. Generate stimulus to produce the characterization decks
3. Simulate the decks using a circuit simulator
4. Gather the simulation output
5. Write this data into standard models, like Liberty?, Verilog, or IBIS

Synopsys offer PrimeLib and NanoTime as solutions for library characterization. 

The PrimeLib solution includes a comprehensive array of library characterization and quality assurance (QA) capabilities that are tuned to produce PrimeTime? signoff-quality libraries with maximum throughput on available compute resources. The innovative technologies encompassing PrimeLib utilize embedded gold reference SPICE engines to provide a characterization speed-up of advanced Liberty models used by PrimeTime static timing analysis (STA) to accurately account for effects seen in ultra-low-voltage FinFET processes that impact timing. This includes PrimeTime parametric on-chip variation (POCV), advanced waveform propagation (AWP), and electromigration (EM) analysis. PrimeLib is cloud-ready, and with its optimized scaling technology accelerates throughput on cloud or on an on-premise cluster. 

NanoTime, the key foundry-certified, golden signoff solution for transistor-level design, performs transistor-level static timing, signal integrity, and process variation analysis for complex custom designs such as CPU datapaths, register files, embedded memories, and analog mixed-signal IP blocks.  For advanced-node designs, such as those using FinFETs, the cost of silicon failure is very significant, making signoff analysis critical to ensure that the design is free from fatal timing and noise problems. Complementing dynamic simulation, NanoTime can exhaustively check for all internal timing and noise interactions. It creates block-level timing models that can be used with PrimeTime for full-chip signoff. NanoTime integrates seamlessly with the Synopsys Custom Compiler? custom design environment and with StarRC? Custom Ultra+ to read layout parasitics. It can also leverage Synopsys simulators HSPICE and FineSim to deliver the highest accuracy.