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As the name implies, PVT sensors represent embedded analog IP blocks that are typically integrated into SoCs with the goal of sensing the process variability and operating environment of the chip. These devices exploit the fact that certain measurable characteristics of a semiconductor device change depending on levels of activity, due to variable software operation or CPU loading, and also from environmental conditions.

For example, the voltage across a diode increases at a known rate as temperature changes. By precisely amplifying this voltage change, an analog signal can be generated that is directly proportional to the local temperature experienced by the diode.

Voltage sensors can use comparator circuits (e.g., op amps) to compare a voltage level to a known reference voltage. Reference voltage-free techniques are also possible by measuring how a test circuit¡¯s performance changes; for example, latency is one characteristic that can be considered, since the change in latency as a function of voltage is known.

A process sensor will use multiple techniques to determine if the particular piece of silicon being used for the SoC is fast, typical, or slow for logic devices.

Embedded PVT sensors are useful during the test/bring-up phase of SoC development and during the deployment of the part in the field. During the test/bring-up phase, PVT sensors support silicon characterization and binning. They are also used to monitor on-chip variation to validate assumptions made during the design phase. In addition, PVT sensors help to validate power reduction methods such as digital voltage and frequency scaling (DVFS) and adaptive voltage scaling (AVS). A critical parameter for SoCs, power must remain in the target window for two primary reasons:

1. To meet system-level power specifications, which are typically a major competitive mandate.
2. To meet the heat dissipation specifications for which the chip and package were designed. Exceeding these metrics can result in poor performance and device failure.

After the test/bring-up phase, embedded PVT sensors continue to provide important information about chip operation in the field. The data collected by these devices can be analyzed locally on-chip to optimize performance and security of the design. The data can also be communicated to the cloud via various on-chip interfaces where more complex analysis can be done. Data from many devices assembled in the cloud allows analysis on aggregated system performance.

These types of analyses are focused on two primary goals:

1. Keep the device performing as originally intended
2. Identify and address unpredicted device issues

With regard to the first item, changes in operating conditions in the field (typically voltage and temperature) can impact device performance. Also, as semiconductor devices age, their performance degrades. Embedded sensors can detect these conditions and implement corrective action to re-center device performance.

With regard to the second item, age or environmentally induced chip failures can occur. Embedded sensors can detect these conditions and on-board logic can implement the appropriate corrective action before catastrophic failures occur. Another form of an unpredicted device issue is a security breach. Many such events have a ¡°signature¡± indicating they are occurring. Embedded sensors can detect these signatures and on-board logic can take appropriate actions. All these events can also be communicated to the cloud, providing detailed information about system operation in the field.

These tasks are all part of the growing Silicon Lifecycle Management discipline.

Embedded PVT sensors provide a level of visibility into SoC operation that is simply unavailable any other way. During the test/bring-up phase, the level of detail regarding SoC operating conditions is greatly enhanced. When an SoC is connected to a production test system, test stimulus can be applied to the inputs of the device and results can be read on the outputs of the device. Environmental conditions such as voltage, ambient temperature, and package/chip temperature can also be measured and controlled. Thanks to scan chain testing, the internal nodes of the circuit can also be controlled and observed.

While very useful, there is another important variable that cannot be measured using this approach ¨C on-chip variation, being a parameter that detrimentally increases with smaller scale technology nodes (i.e., 16nm down to 3nm). For SoCs implemented in advanced technology nodes, there is significant performance variability across the silicon die. Local voltage, or IR drop, effects can cause a chip¡¯s performance to move out of its specifications. Temperature profiles also vary across the silicon die, causing local heating and stress. Embedded PVT sensors allow these effects to be measured and controlled in a fine-grained way, resulting in enhanced device performance and reliability.

Thanks to cloud-based analytics, additional information is available to drive substantial value-added services. Enhanced security measures can be implemented. Sophisticated preventative maintenance procedures can also be deployed, potentially avoiding system downtime and saving money. Performance monitoring is also a critical item for applications such as autonomous driving. These technologies will allow devices to last for longer periods of time while delivering improved and more reliable performance.

All of these tasks are part of the Silicon Lifecycle Management process.