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Parametric On-Chip Variation

On-chip variation (OCV) effects continue to increase with shrinking geometry nodes and lower voltages. Applying a flat global margin across the entire chip can lead to overdesign, reduced design performance, and longer timing closure schedules. While the PrimeTime Advanced OCV (AOCV) technology takes advantage of improved device-level variation modeling techniques to provide the right balance between accuracy and performance for planar process node designs, the more advanced Parametric OCV (POCV) provides the necessary technology to accurately analyze FinFET designs.

HyperScale

When TAT and capacity are critical, HyperScale is a must. PrimeTime HyperScale technology brings smarter, hierarchical timing analysis to mainstream designs, allowing teams to take advantage of a more efficient block-level methodology and smaller, more readily available machines. This technology extends PrimeTime static timing analysis to support designs beyond 500 million instances, while delivering 2 to 5X faster runtimes for the full chip timing analysis using 2 to 5X smaller memory footprint compared with flat analysis. PrimeTime HyperScale technology enables hierarchical STA by performing accurate block level timing analysis in the context of the top-level. This technology offers faster top and block timing convergence, timing reuse, and scalability to complete daily analysis on any size designs.

Multi-scenario Analysis

PrimeTime offers several technologies to accelerate both the analysis and debug of multi-scenario designs. Going beyond multi-scenario analysis, PrimeTime mode merging and simultaneous multi-voltage aware analysis (SMVA) actively work to reduce the number of scenarios to be analyzed. This allows users to reduce the hardware resources and turnaround time for multi-scenario analysis, while maintaining signoff quality timing correlation. Distributed Multi-Scenario Analysis (DMSA) and Interactive Multi-Scenario Analysis (IMSA) allow users to efficiently setup and debug multi-scenario runs.

ECO Guidance

PrimeTime ECO guidance technology uses signoff-driven analysis to efficiently identify ECO changes for timing and DRC fixes at the block or chip level, shortening tape-out schedules by weeks. Multi-scenario, physically-aware ECO guidance reduces the time and iterations required to reach timing closure on congested designs. PrimeTime can provide critical optimizations for clock trees, noise reduction, and spare cell ECOs, while using 5X less memory and compute resources. PrimeTime ECO can take advantage of positive timing slack for leakage power reduction opportunities. In addition, PrimeTime supports incremental ECO changes within the Synopsys Design Platform, further reducing turnaround time.

Timing Constraint Consistency

The rapid increase in design size and complexity, the advent of hierarchical block-level analysis, as well as the widespread reuse of IP design blocks, has led to a major increase in the size and complexity of timing constraint specification files. Not only are the constraints getting more complex, it is important to make sure the constraints are consistent across the design, across the hierarchy, and across the implementation flow. Ensuring high-quality timing constraints is paramount to efficient design implementation, especially during handoffs between teams. Incomplete, inconsistent or conflicting constraints can cause optimization, implementation and analysis tools to run ineffectively or to fail to converge. To address this challenge, PrimeTime provides a comprehensive set of rule checks designed to ensure constraint consistency and to maximize the efficiency of implementation and timing analysis.