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In this AI-driven era of pervasive intelligence, our silicon and systems customers face unprecedented pressure to deliver the increasing compute performance?required to train LLM-based AI systems as demands double every six months. Moreover, they¡¯re being challenged to achieve sustainable computing - exponential performance gains with increasing power efficiency. Traditional reliance on Moore's Law is no longer sufficient, as recent node transitions no longer consistently deliver the expected 2X improvement in performance, power, and area. 

These challenges are compounded by an and increasing design complexity as we march towards trillion-transistor systems by the end of this decade. And yet remarkably ¨C contrary to these trends ¨C the pace of semiconductor innovation is accelerating.

Just look at recent announcements from and at Computex. These major chip makers not only showcased new AI processors featuring hundreds of billions of transistors and faster, denser memory, destined for leading-edge manufacturing nodes, they also put a spotlight on their increasing speed of innovation. Despite mounting complexity, product refresh cycles for new AI processors are contracting from 18-24 months to 12 months. 

Trends in AI Chip Design

How is this breakneck, annual rhythm of new AI processors possible? Synopsys is at the heart of multiple contributing factors. Let¡¯s take a closer look. 

• AI-driven EDA: ?EDA software is the mission-critical enabler of every step in the R&D process from architecture and verification to implementation and manufacturing. Over the last decade, Synopsys has delivered increasing levels of automation across the entire EDA stack through?our unique hyper-convergence approach. Today, our pioneering infusion of AI across our full EDA stack is increasingly automating the design process to drive step-function gains in engineering productivity and silicon quality. Our? Synopsys.ai??suite including AI-driven optimization, data analytics, and?LLM-based generative?AI with collaborative capabilities including expert tool guidance and collateral generation, is delivering dramatically accelerating turnaround times across the EDA flow from digital, analog and 3D design to verification and test.?
  
  
• Accelerated Computing: In addition to engineering AI capabilities into our products, we are also helping our customers realize tremendous time savings by rewriting our tools to take advantage of . Using GPU and CPU + GPU architectures to power compute-intensive EDA workloads can deliver dramatic (10x to 15x) runtime gains spanning design, functional verification, circuit simulation, and more. Accelerated computing is particularly appealing for customers dealing with large analog circuits, like memory.