Cloud native EDA tools & pre-optimized hardware platforms
Synopsys Verification IP (VIP) for JEDEC GDDR6 provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of GDDR6 based designs. The VIP is based on next generation architecture and implemented in native SystemVerilog/UVM. VIP is natively integrated with Verdi? Protocol and Memory Analyzer for easy and fast debug and Verdi Performance Analyzer to find and fix performance bottle necks.
Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys¡¯ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.
Synopsys VIP supports generic JEDEC part numbers with densities ranging from 8Gb to 32Gb, data rates up to 8800 Mbps, and bus width from X4 to X16. It supports core timings according to specific frequencies and densities. Synopsys collaborates with leading memory vendors, including Samsung, SK Hynix, Micron, and Nanya for support of specific vendor part numbers, as they are made available. It also provides a configuration to model all possible JEDEC part numbers virtually. The virtual part number feature enhances productivity, as user need not to request and wait for delivery of the required part number from Synopsys.