Cloud native EDA tools & pre-optimized hardware platforms
Synopsys Verification IP (VIP) for HBM provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of HBM based designs.
Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys¡¯ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.
All commands including refresh management commands
All Test instructions
All HBM3 trainings:
Data skew and Data bus inversion
Command and Data parity
All mode register support covering all settings
Other features:
All commands:
All Test instructions
Loopback Test Modes:
Data Bus inversion and Data Masking
Command and Data parity
All mode register support covering all settings
Other features:
Clock Jitter
RDQS Jitter
RDQS Duty cycle adjustment
Callbacks for data corruption
Static and dynamic reconfiguration for timing and configuration settings
Data Eye damage
Board delay modelling
Skew Support (twdqs2dq_i and twdqs2dq_o)
Functional, checker and timing coverage
Is_valid checkers
Hierarchal Verification Plan
Tested with vendor part numbers
Analysis port for score boarding
Verdi protocol Analyzer and Performance Analyzer