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About VC SpyGlass IDC
VC SpyGlass? IDC is built on the highly scalable VC SpyGlass RTL Signoff platform. It addresses the challenging issue of verifying register optimizations in system-on-chip (SoC) designs. Traditional implementation tools list optimized registers without explaining the reasoning, causing designers to spend months identifying root causes. This solution provides an early-stage, comprehensive methodology for flagging registers likely to be optimized during synthesis. By enabling high debug productivity and identifying potential logic congestion early, VC SpyGlass helps streamline the design cycle and prevent costly respins, ensuring more predictable and efficient design outcomes.
Key Benefits
Identify Critical RTL Issues Earlier
Avoid Extra Synthesis Cycles
Intuitive Verdi Debugging
Enabling Ease of Use and Functionality
- Reuse existing VC SpyGlass setup for easy bring-up
- Accurate determination of optimized registers with best correlation with Synopsys Fusion Compiler
- Advanced debug capabilities with integrated waveform viewer within Synopsys Verdi
- Highest performance for billion+ gate designs for faster signoff
- Consolidated reporting of optimized registers
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