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Using many advanced algorithms and analysis techniques, the SpyGlass? platform provides designers with insight about their design, early in the process at RTL. It functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.
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SpyGlass for FPGA Designs
Among the many verification challenges confronting FPGA designers, clock domain crossings (CDC) ranks near the top in difficulty. Today¡¯s designs have dozens of asynchronous clock domains, making it difficult to verify using conventional simulation or static timing analysis (STA). The SpyGlass? product family is the industry standard for early design analysis with the most in-depth analysis at the RTL design phase. SpyGlass provides an integrated solution for analysis, debug and fixing with a comprehensive set of capabilities for structural and electrical issues all tied to the RTL description of design.