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Synopsys’ solution to efficiently design and implement your own application-specific instruction-set processor (ASIP) when you can’t find suitable processor IP, or when hardware implementations require more flexibility.
This bi-annual newsletter provides you with easy access to ASIP-related resources.
In the T-2022.06 and U-2022.12 ASIP Designer? releases and their ASIP Programmer? derivatives, several enhancements have been added to the ChessDE graphical IDE to improve the user experience and increase productivity. These enhancements include easier context-aware navigation in the editor, various new visualization capabilities in profiling, and more user-friendly feedback of the compiler’s scheduler.
ASIP Designer and ASIP Programmer now include a language server that provides language-specific smart features for C/C++ application code. The ChessDE GUI can communicate with this server through a specific language server protocol.
Once this feature is enabled in the ChessDE preferences menu, the context menu of the editor then contains an additional submenu Language server, as shown in Figure 1. This menu allows the user to quickly navigate through the source code to the declarations, definitions, or implementations of the current symbol, get detailed information on it, or speed-up editing via auto-completion of existing symbols.
Figure 1: ChessDE editor using a language server protocol
The ChessDE profiler now includes cycle bar charts in call-tree tables, which helps identify the most time-consuming parts of a program more quickly. An example is shown in Figure 2.
Figure 2: Cycle bar charts in call-tree table
As an even more concise and intuitive visualization of this information, ChessDE is now able to generate flamegraphs, as shown in Figure 3.
Figure 3: Example flamegraph (bottom) and corresponding configuration options (top)
The vertical axis contains the call tree information. Functions in lower rows are deeper in the call tree. The horizontal axis represents the time spent in each function in the call tree as a fraction of the total execution time.
Flamegraph information can be exported in xml format and hence be used as a reference to be compared against, to explore the effect of an architectural change. If a reference XML file is specified, the tool generates a differential flamegraph as shown Figure 4. A function that performs better with respect to the reference would be colored blue, a function that became slower is colored red.
Figure 4: Differential flamegraph
ChessDE now supports the export of profiling data in the Callgrind profile format. The resulting file can then be visualized using Cachegrind, an open-source tool that users can install separately from ASIP Designer. On most Linux platforms, it is available as KCachegrind. There is also a Windows port known as QCachegrind.
Figure 5 shows the configuration of profiling data in ChessDE (bottom left), and the resulting Cachegrind visualization of the function profile (top left), call graph (top right), and highlighted source and assembly code (bottom right).
Figure 5: Visualization of ASIP profiling information in Cachegrind
The compiler’s optional scheduling reports have been enhanced by showing the actual assembly syntax and the involved registers of the scheduled instructions. This enables developers to better link scheduler feedback to the nML processor model, without having to dive deep into the internal representation of operations in a scheduling graph. This applies to the textual scheduling reports as well as to their graphical representation, an example of which is shown in Figure 6.
Figure 6: Visualization of a scheduling graph
Since the last edition of this newsletter, we have launched two new feature releases of ASIP Designer, in June 2022 and December 2022, providing various enhancements and extensions. The following is an extract of accumulated enhancements from both releases, sorted by categories (customers can refer to the official Release Notes for a comprehensive list).
Click on each tab for additional information about that new feature
Designers can choose from an extensive library of example processor models provided as nML source code. In combination with ASIP Designer, these models can be used as a starting point for architectural exploration and customer-specific production designs. In the 2022.06 release there have been following updates:
ASIP Designer comes with a unique and patented compiler solution, with the compiler automatically retargeting itself to the processor architecture. This eliminates any need for compiler backend customization by the user. Releases 2022.06 and 2022.12 offer the following enhancements: